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sconv: avoid multiply in ARM NEON s16->float conversion

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Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net>
This commit is contained in:
Peter Meerwald 2013-07-02 14:06:04 +02:00 • committed by Tanu Kaskinen
parent 40c3c117e7
commit 736e041980
1 changed files with 4 additions and 8 deletions
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12
src/pulsecore/sconv_neon.c
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@ -61,19 +61,14 @@ static void pa_sconv_s16le_from_f32ne_neon(unsigned n, const float *src, int16_t
static void pa_sconv_s16le_to_f32ne_neon(unsigned n, const int16_t *src, float *dst) { static void pa_sconv_s16le_to_f32ne_neon(unsigned n, const int16_t *src, float *dst) {
unsigned i = n & 3; unsigned i = n & 3;
const float invscale = 1.0f / (1 << 15);
__asm__ __volatile__ ( __asm__ __volatile__ (
"movs %[n], %[n], lsr #2 \n\t" "movs %[n], %[n], lsr #2 \n\t"
"beq 2f \n\t" "beq 2f \n\t"
"vdup.f32 q1, %[invscale] \n\t"
"1: \n\t" "1: \n\t"
"vld1.16 {d0}, [%[src]]! \n\t" "vld1.16 {d0}, [%[src]]! \n\t"
"vmovl.s16 q0, d0 \n\t" /* widen */ "vmovl.s16 q0, d0 \n\t" /* widen */
"vcvt.f32.s32 q0, q0 \n\t" /* f32<-s32 */ "vcvt.f32.s32 q0, q0, #15 \n\t" /* f32<-s32 and divide by (1<<15) */
"vmul.f32 q0, q0, q1 \n\t"
"subs %[n], %[n], #1 \n\t" "subs %[n], %[n], #1 \n\t"
"vst1.32 {q0}, [%[dst]]! \n\t" "vst1.32 {q0}, [%[dst]]! \n\t"
"bgt 1b \n\t" "bgt 1b \n\t"
@ -81,11 +76,12 @@ static void pa_sconv_s16le_to_f32ne_neon(unsigned n, const int16_t *src, float *
"2: \n\t" "2: \n\t"
: [dst] "+r" (dst), [src] "+r" (src), [n] "+r" (n) /* output operands (or input operands that get modified) */ : [dst] "+r" (dst), [src] "+r" (src), [n] "+r" (n) /* output operands (or input operands that get modified) */
: [invscale] "r" (invscale) /* input operands */ : /* input operands */
: "memory", "cc", "q0", "q1" /* clobber list */ : "memory", "cc", "q0" /* clobber list */
); );
/* leftovers */ /* leftovers */
const float invscale = 1.0f / (1 << 15);
while (i--) { while (i--) {
*dst++ = *src++ * invscale; *dst++ = *src++ * invscale;
} }