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934ab3036e
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198 lines
6.2 KiB
C
198 lines
6.2 KiB
C
/* Spa */
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/* SPDX-FileCopyrightText: Copyright © 2019 Wim Taymans */
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/* SPDX-License-Identifier: MIT */
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#include "resample-native-impl.h"
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#include <arm_neon.h>
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static inline void inner_product_neon(float *d, const float * SPA_RESTRICT s,
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const float * SPA_RESTRICT taps, uint32_t n_taps)
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{
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unsigned int remainder = n_taps % 16;
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n_taps = n_taps - remainder;
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#ifdef __aarch64__
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asm volatile(
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" cmp %[n_taps], #0\n"
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" bne 1f\n"
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" ld1 {v4.4s}, [%[taps]], #16\n"
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" ld1 {v8.4s}, [%[s]], #16\n"
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" subs %[remainder], %[remainder], #4\n"
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" fmul v0.4s, v4.4s, v8.4s\n"
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" bne 4f\n"
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" b 5f\n"
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"1:"
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" ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [%[taps]], #64\n"
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" ld1 {v8.4s, v9.4s, v10.4s, v11.4s}, [%[s]], #64\n"
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" subs %[n_taps], %[n_taps], #16\n"
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" fmul v0.4s, v4.4s, v8.4s\n"
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" fmul v1.4s, v5.4s, v9.4s\n"
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" fmul v2.4s, v6.4s, v10.4s\n"
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" fmul v3.4s, v7.4s, v11.4s\n"
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" beq 3f\n"
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"2:"
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" ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [%[taps]], #64\n"
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" ld1 {v8.4s, v9.4s, v10.4s, v11.4s}, [%[s]], #64\n"
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" subs %[n_taps], %[n_taps], #16\n"
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" fmla v0.4s, v4.4s, v8.4s\n"
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" fmla v1.4s, v5.4s, v9.4s\n"
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" fmla v2.4s, v6.4s, v10.4s\n"
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" fmla v3.4s, v7.4s, v11.4s\n"
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" bne 2b\n"
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"3:"
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" fadd v4.4s, v0.4s, v1.4s\n"
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" fadd v5.4s, v2.4s, v3.4s\n"
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" cmp %[remainder], #0\n"
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" fadd v0.4s, v4.4s, v5.4s\n"
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" beq 5f\n"
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"4:"
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" ld1 {v6.4s}, [%[taps]], #16\n"
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" ld1 {v10.4s}, [%[s]], #16\n"
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" subs %[remainder], %[remainder], #4\n"
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" fmla v0.4s, v6.4s, v10.4s\n"
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" bne 4b\n"
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"5:"
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" faddp v0.4s, v0.4s, v0.4s\n"
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" faddp v0.2s, v0.2s, v0.2s\n"
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" str s0, [%[d]]\n"
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: [d] "+r" (d), [s] "+r" (s), [taps] "+r" (taps),
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[n_taps] "+r" (n_taps), [remainder] "+r" (remainder)
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:
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: "cc", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
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"v9", "v10", "v11");
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#else
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asm volatile (
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" cmp %[n_taps], #0\n"
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" bne 1f\n"
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" vld1.32 {q4}, [%[taps] :128]!\n"
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" vld1.32 {q8}, [%[s]]!\n"
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" subs %[remainder], %[remainder], #4\n"
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" vmul.f32 q0, q4, q8\n"
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" bne 4f\n"
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" b 5f\n"
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"1:"
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" vld1.32 {q4, q5}, [%[taps] :128]!\n"
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" vld1.32 {q8, q9}, [%[s]]!\n"
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" vld1.32 {q6, q7}, [%[taps] :128]!\n"
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" vld1.32 {q10, q11}, [%[s]]!\n"
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" subs %[n_taps], %[n_taps], #16\n"
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" vmul.f32 q0, q4, q8\n"
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" vmul.f32 q1, q5, q9\n"
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" vmul.f32 q2, q6, q10\n"
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" vmul.f32 q3, q7, q11\n"
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" beq 3f\n"
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"2:"
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" vld1.32 {q4, q5}, [%[taps] :128]!\n"
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" vld1.32 {q8, q9}, [%[s]]!\n"
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" vld1.32 {q6, q7}, [%[taps] :128]!\n"
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" vld1.32 {q10, q11}, [%[s]]!\n"
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" subs %[n_taps], %[n_taps], #16\n"
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" vmla.f32 q0, q4, q8\n"
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" vmla.f32 q1, q5, q9\n"
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" vmla.f32 q2, q6, q10\n"
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" vmla.f32 q3, q7, q11\n"
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" bne 2b\n"
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"3:"
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" vadd.f32 q4, q0, q1\n"
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" vadd.f32 q5, q2, q3\n"
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" cmp %[remainder], #0\n"
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" vadd.f32 q0, q4, q5\n"
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" beq 5f\n"
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"4:"
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" vld1.32 {q6}, [%[taps] :128]!\n"
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" vld1.32 {q10}, [%[s]]!\n"
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" subs %[remainder], %[remainder], #4\n"
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" vmla.f32 q0, q6, q10\n"
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" bne 4b\n"
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"5:"
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" vadd.f32 d0, d0, d1\n"
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" vpadd.f32 d0, d0, d0\n"
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" vstr d0, [%[d]]\n"
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: [d] "+r" (d), [s] "+r" (s), [taps] "+r" (taps),
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[n_taps] "+l" (n_taps), [remainder] "+l" (remainder)
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:
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: "cc", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8",
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"q9", "q10", "q11");
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#endif
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}
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static inline void inner_product_ip_neon(float *d, const float * SPA_RESTRICT s,
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const float * SPA_RESTRICT t0, const float * SPA_RESTRICT t1, float x,
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uint32_t n_taps)
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{
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#ifdef __aarch64__
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asm volatile(
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" dup v10.4s, %w[x]\n"
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" ld1 {v4.4s, v5.4s}, [%[t0]], #32\n"
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" ld1 {v8.4s, v9.4s}, [%[s]], #32\n"
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" ld1 {v6.4s, v7.4s}, [%[t1]], #32\n"
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" subs %[n_taps], %[n_taps], #8\n"
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" fmul v0.4s, v4.4s, v8.4s\n"
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" fmul v1.4s, v5.4s, v9.4s\n"
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" fmul v2.4s, v6.4s, v8.4s\n"
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" fmul v3.4s, v7.4s, v9.4s\n"
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" beq 3f\n"
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"2:"
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" ld1 {v4.4s, v5.4s}, [%[t0]], #32\n"
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" ld1 {v8.4s, v9.4s}, [%[s]], #32\n"
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" ld1 {v6.4s, v7.4s}, [%[t1]], #32\n"
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" subs %[n_taps], %[n_taps], #8\n"
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" fmla v0.4s, v4.4s, v8.4s\n"
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" fmla v1.4s, v5.4s, v9.4s\n"
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" fmla v2.4s, v6.4s, v8.4s\n"
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" fmla v3.4s, v7.4s, v9.4s\n"
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" bne 2b\n"
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"3:"
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" fadd v0.4s, v0.4s, v1.4s\n" /* sum[0] */
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" fadd v2.4s, v2.4s, v3.4s\n" /* sum[1] */
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" fsub v2.4s, v2.4s, v0.4s\n" /* sum[1] -= sum[0] */
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" fmla v0.4s, v2.4s, v10.4s\n" /* sum[0] += sum[1] * x */
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" faddp v0.4s, v0.4s, v0.4s\n"
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" faddp v0.2s, v0.2s, v0.2s\n"
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" str s0, [%[d]]\n"
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: [d] "+r" (d), [s] "+r" (s), [t0] "+r" (t0), [t1] "+r" (t1),
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[n_taps] "+r" (n_taps), [x] "+r" (x)
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:
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: "cc", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
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"v9", "v10");
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#else
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asm volatile(
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" vdup.32 q10, %[x]\n"
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" vld1.32 {q4, q5}, [%[t0] :128]!\n"
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" vld1.32 {q8, q9}, [%[s]]!\n"
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" vld1.32 {q6, q7}, [%[t1] :128]!\n"
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" subs %[n_taps], %[n_taps], #8\n"
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" vmul.f32 q0, q4, q8\n"
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" vmul.f32 q1, q5, q9\n"
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" vmul.f32 q2, q6, q8\n"
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" vmul.f32 q3, q7, q9\n"
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" beq 3f\n"
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"2:"
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" vld1.32 {q4, q5}, [%[t0] :128]!\n"
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" vld1.32 {q8, q9}, [%[s]]!\n"
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" vld1.32 {q6, q7}, [%[t1] :128]!\n"
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" subs %[n_taps], %[n_taps], #8\n"
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" vmla.f32 q0, q4, q8\n"
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" vmla.f32 q1, q5, q9\n"
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" vmla.f32 q2, q6, q8\n"
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" vmla.f32 q3, q7, q9\n"
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" bne 2b\n"
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"3:"
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" vadd.f32 q0, q0, q1\n" /* sum[0] */
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" vadd.f32 q2, q2, q3\n" /* sum[1] */
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" vsub.f32 q2, q2, q0\n" /* sum[1] -= sum[0] */
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" vmla.f32 q0, q2, q10\n" /* sum[0] += sum[1] * x */
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" vadd.f32 d0, d0, d1\n"
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" vpadd.f32 d0, d0, d0\n"
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" vstr d0, [%[d]]\n"
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: [d] "+r" (d), [s] "+r" (s), [t0] "+r" (t0), [t1] "+r" (t1),
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[n_taps] "+l" (n_taps), [x] "+l" (x)
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:
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: "cc", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8",
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"q9", "q10");
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#endif
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}
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MAKE_RESAMPLER_FULL(neon);
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MAKE_RESAMPLER_INTER(neon);
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