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9846e0cb7a
The codec may need to take into account endpoint preferred QoS values, so parse this information and pass it to the codec's get_qos. All the QoS struct values need to be set, as otherwise BlueZ may pass uninitialized zero values over the air, which devices can reject. This does not apply to CIG/CIS ids, which are automatically allocated by default. Fixes connecting to nrf5340 devkit, which requires a valid TargetLatency value.
142 lines
5.5 KiB
C
142 lines
5.5 KiB
C
/* Spa BAP codec API
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*
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* Copyright © 2022 Collabora
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef SPA_BLUEZ5_BAP_CODEC_CAPS_H_
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#define SPA_BLUEZ5_BAP_CODEC_CAPS_H_
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#define BAP_CODEC_LC3 0x06
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#define LC3_TYPE_FREQ 0x01
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#define LC3_FREQ_8KHZ (1 << 0)
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#define LC3_FREQ_11KHZ (1 << 1)
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#define LC3_FREQ_16KHZ (1 << 2)
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#define LC3_FREQ_22KHZ (1 << 3)
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#define LC3_FREQ_24KHZ (1 << 4)
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#define LC3_FREQ_32KHZ (1 << 5)
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#define LC3_FREQ_44KHZ (1 << 6)
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#define LC3_FREQ_48KHZ (1 << 7)
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#define LC3_FREQ_ANY (LC3_FREQ_8KHZ | \
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LC3_FREQ_11KHZ | \
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LC3_FREQ_16KHZ | \
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LC3_FREQ_22KHZ | \
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LC3_FREQ_24KHZ | \
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LC3_FREQ_32KHZ | \
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LC3_FREQ_44KHZ | \
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LC3_FREQ_48KHZ)
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#define LC3_TYPE_DUR 0x02
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#define LC3_DUR_7_5 (1 << 0)
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#define LC3_DUR_10 (1 << 1)
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#define LC3_DUR_ANY (LC3_DUR_7_5 | \
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LC3_DUR_10)
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#define LC3_TYPE_CHAN 0x03
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#define LC3_CHAN_1 (1 << 0)
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#define LC3_CHAN_2 (1 << 1)
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#define LC3_TYPE_FRAMELEN 0x04
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#define LC3_TYPE_BLKS 0x05
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/* LC3 config parameters */
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#define LC3_CONFIG_FREQ_8KHZ 0x01
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#define LC3_CONFIG_FREQ_11KHZ 0x02
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#define LC3_CONFIG_FREQ_16KHZ 0x03
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#define LC3_CONFIG_FREQ_22KHZ 0x04
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#define LC3_CONFIG_FREQ_24KHZ 0x05
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#define LC3_CONFIG_FREQ_32KHZ 0x06
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#define LC3_CONFIG_FREQ_44KHZ 0x07
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#define LC3_CONFIG_FREQ_48KHZ 0x08
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#define LC3_CONFIG_DURATION_7_5 0x00
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#define LC3_CONFIG_DURATION_10 0x01
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#define LC3_CONFIG_CHNL_NOT_ALLOWED 0x00000000
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#define LC3_CONFIG_CHNL_FL 0x00000001 /* front left */
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#define LC3_CONFIG_CHNL_FR 0x00000002 /* front right */
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#define LC3_CONFIG_CHNL_FC 0x00000004 /* front center */
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#define LC3_CONFIG_CHNL_LFE 0x00000008 /* LFE */
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#define LC3_CONFIG_CHNL_BL 0x00000010 /* back left */
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#define LC3_CONFIG_CHNL_BR 0x00000020 /* back right */
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#define LC3_CONFIG_CHNL_FLC 0x00000040 /* front left center */
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#define LC3_CONFIG_CHNL_FRC 0x00000080 /* front right center */
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#define LC3_CONFIG_CHNL_BC 0x00000100 /* back center */
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#define LC3_CONFIG_CHNL_LFE2 0x00000200 /* LFE 2 */
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#define LC3_CONFIG_CHNL_SL 0x00000400 /* side left */
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#define LC3_CONFIG_CHNL_SR 0x00000800 /* side right */
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#define LC3_CONFIG_CHNL_TFL 0x00001000 /* top front left */
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#define LC3_CONFIG_CHNL_TFR 0x00002000 /* top front right */
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#define LC3_CONFIG_CHNL_TFC 0x00004000 /* top front center */
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#define LC3_CONFIG_CHNL_TC 0x00008000 /* top center */
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#define LC3_CONFIG_CHNL_TBL 0x00010000 /* top back left */
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#define LC3_CONFIG_CHNL_TBR 0x00020000 /* top back right */
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#define LC3_CONFIG_CHNL_TSL 0x00040000 /* top side left */
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#define LC3_CONFIG_CHNL_TSR 0x00080000 /* top side right */
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#define LC3_CONFIG_CHNL_TBC 0x00100000 /* top back center */
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#define LC3_CONFIG_CHNL_BFC 0x00200000 /* bottom front center */
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#define LC3_CONFIG_CHNL_BFL 0x00400000 /* bottom front left */
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#define LC3_CONFIG_CHNL_BFR 0x00800000 /* bottom front right */
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#define LC3_CONFIG_CHNL_FLW 0x01000000 /* front left wide */
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#define LC3_CONFIG_CHNL_FRW 0x02000000 /* front right wide */
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#define LC3_CONFIG_CHNL_LS 0x04000000 /* left surround */
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#define LC3_CONFIG_CHNL_RS 0x08000000 /* right surround */
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#define LC3_MAX_CHANNELS 28
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typedef struct {
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uint8_t rate;
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uint8_t frame_duration;
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uint32_t channels;
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uint16_t framelen;
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uint8_t n_blks;
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} __attribute__ ((packed)) bap_lc3_t;
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#define BT_ISO_QOS_CIG_UNSET 0xff
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#define BT_ISO_QOS_CIS_UNSET 0xff
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#define BT_ISO_QOS_TARGET_LATENCY_LOW 0x01
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#define BT_ISO_QOS_TARGET_LATENCY_BALANCED 0x02
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#define BT_ISO_QOS_TARGET_LATENCY_RELIABILITY 0x03
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struct bap_endpoint_qos {
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uint8_t framing;
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uint8_t phy;
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uint8_t retransmission;
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uint16_t latency;
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uint32_t delay_min;
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uint32_t delay_max;
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uint32_t preferred_delay_min;
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uint32_t preferred_delay_max;
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};
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struct bap_codec_qos {
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uint32_t interval;
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uint8_t framing;
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uint8_t phy;
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uint16_t sdu;
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uint8_t retransmission;
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uint16_t latency;
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uint32_t delay;
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uint8_t target_latency;
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};
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#endif
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