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https://gitlab.freedesktop.org/pipewire/pipewire.git
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7e9e261fa6
Add pw_conf_section_update_props_rules() that will not only update the properties of a section but wil also apply rules in section.rules and match against the context properties. Use this by default when using pw_context_conf_update_props(). Add a new method to get a string name of the VM type. Place the cpu.vm.name in the context properties. This makes it possible to deprecate the vm.overrides with something more flexible based on rules. Update the conf files and docs to refect this.
188 lines
5.3 KiB
C
188 lines
5.3 KiB
C
/* Simple Plugin API */
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/* SPDX-FileCopyrightText: Copyright © 2018 Wim Taymans */
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/* SPDX-License-Identifier: MIT */
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#ifndef SPA_CPU_H
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#define SPA_CPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdarg.h>
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#include <spa/utils/defs.h>
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#include <spa/utils/hook.h>
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/** \defgroup spa_cpu CPU
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* Querying CPU properties
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*/
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/**
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* \addtogroup spa_cpu
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* \{
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*/
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/**
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* The CPU features interface
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*/
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#define SPA_TYPE_INTERFACE_CPU SPA_TYPE_INFO_INTERFACE_BASE "CPU"
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#define SPA_VERSION_CPU 0
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struct spa_cpu { struct spa_interface iface; };
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/* x86 specific */
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#define SPA_CPU_FLAG_MMX (1<<0) /**< standard MMX */
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#define SPA_CPU_FLAG_MMXEXT (1<<1) /**< SSE integer or AMD MMX ext */
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#define SPA_CPU_FLAG_3DNOW (1<<2) /**< AMD 3DNOW */
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#define SPA_CPU_FLAG_SSE (1<<3) /**< SSE */
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#define SPA_CPU_FLAG_SSE2 (1<<4) /**< SSE2 */
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#define SPA_CPU_FLAG_3DNOWEXT (1<<5) /**< AMD 3DNowExt */
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#define SPA_CPU_FLAG_SSE3 (1<<6) /**< Prescott SSE3 */
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#define SPA_CPU_FLAG_SSSE3 (1<<7) /**< Conroe SSSE3 */
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#define SPA_CPU_FLAG_SSE41 (1<<8) /**< Penryn SSE4.1 */
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#define SPA_CPU_FLAG_SSE42 (1<<9) /**< Nehalem SSE4.2 */
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#define SPA_CPU_FLAG_AESNI (1<<10) /**< Advanced Encryption Standard */
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#define SPA_CPU_FLAG_AVX (1<<11) /**< AVX */
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#define SPA_CPU_FLAG_XOP (1<<12) /**< Bulldozer XOP */
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#define SPA_CPU_FLAG_FMA4 (1<<13) /**< Bulldozer FMA4 */
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#define SPA_CPU_FLAG_CMOV (1<<14) /**< supports cmov */
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#define SPA_CPU_FLAG_AVX2 (1<<15) /**< AVX2 */
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#define SPA_CPU_FLAG_FMA3 (1<<16) /**< Haswell FMA3 */
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#define SPA_CPU_FLAG_BMI1 (1<<17) /**< Bit Manipulation Instruction Set 1 */
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#define SPA_CPU_FLAG_BMI2 (1<<18) /**< Bit Manipulation Instruction Set 2 */
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#define SPA_CPU_FLAG_AVX512 (1<<19) /**< AVX-512 */
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#define SPA_CPU_FLAG_SLOW_UNALIGNED (1<<20) /**< unaligned loads/stores are slow */
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/* PPC specific */
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#define SPA_CPU_FLAG_ALTIVEC (1<<0) /**< standard */
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#define SPA_CPU_FLAG_VSX (1<<1) /**< ISA 2.06 */
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#define SPA_CPU_FLAG_POWER8 (1<<2) /**< ISA 2.07 */
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/* ARM specific */
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#define SPA_CPU_FLAG_ARMV5TE (1 << 0)
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#define SPA_CPU_FLAG_ARMV6 (1 << 1)
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#define SPA_CPU_FLAG_ARMV6T2 (1 << 2)
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#define SPA_CPU_FLAG_VFP (1 << 3)
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#define SPA_CPU_FLAG_VFPV3 (1 << 4)
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#define SPA_CPU_FLAG_NEON (1 << 5)
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#define SPA_CPU_FLAG_ARMV8 (1 << 6)
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#define SPA_CPU_FORCE_AUTODETECT ((uint32_t)-1)
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#define SPA_CPU_VM_NONE (0)
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#define SPA_CPU_VM_OTHER (1 << 0)
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#define SPA_CPU_VM_KVM (1 << 1)
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#define SPA_CPU_VM_QEMU (1 << 2)
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#define SPA_CPU_VM_BOCHS (1 << 3)
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#define SPA_CPU_VM_XEN (1 << 4)
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#define SPA_CPU_VM_UML (1 << 5)
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#define SPA_CPU_VM_VMWARE (1 << 6)
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#define SPA_CPU_VM_ORACLE (1 << 7)
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#define SPA_CPU_VM_MICROSOFT (1 << 8)
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#define SPA_CPU_VM_ZVM (1 << 9)
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#define SPA_CPU_VM_PARALLELS (1 << 10)
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#define SPA_CPU_VM_BHYVE (1 << 11)
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#define SPA_CPU_VM_QNX (1 << 12)
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#define SPA_CPU_VM_ACRN (1 << 13)
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#define SPA_CPU_VM_POWERVM (1 << 14)
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static inline const char *spa_cpu_vm_type_to_string(uint32_t vm_type)
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{
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switch(vm_type) {
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case SPA_CPU_VM_NONE:
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return NULL;
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case SPA_CPU_VM_KVM:
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return "kvm";
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case SPA_CPU_VM_QEMU:
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return "qemu";
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case SPA_CPU_VM_BOCHS:
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return "bochs";
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case SPA_CPU_VM_XEN:
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return "xen";
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case SPA_CPU_VM_UML:
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return "uml";
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case SPA_CPU_VM_VMWARE:
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return "vmware";
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case SPA_CPU_VM_ORACLE:
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return "oracle";
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case SPA_CPU_VM_MICROSOFT:
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return "microsoft";
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case SPA_CPU_VM_ZVM:
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return "zvm";
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case SPA_CPU_VM_PARALLELS:
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return "parallels";
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case SPA_CPU_VM_BHYVE:
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return "bhyve";
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case SPA_CPU_VM_QNX:
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return "qnx";
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case SPA_CPU_VM_ACRN:
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return "acrn";
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case SPA_CPU_VM_POWERVM:
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return "powervm";
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case SPA_CPU_VM_OTHER:
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return "other";
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default:
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return "unknown";
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}
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}
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/**
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* methods
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*/
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struct spa_cpu_methods {
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/** the version of the methods. This can be used to expand this
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structure in the future */
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#define SPA_VERSION_CPU_METHODS 2
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uint32_t version;
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/** get CPU flags */
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uint32_t (*get_flags) (void *object);
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/** force CPU flags, use SPA_CPU_FORCE_AUTODETECT to autodetect CPU flags */
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int (*force_flags) (void *object, uint32_t flags);
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/** get number of CPU cores */
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uint32_t (*get_count) (void *object);
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/** get maximum required alignment of data */
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uint32_t (*get_max_align) (void *object);
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/* check if running in a VM. Since:1 */
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uint32_t (*get_vm_type) (void *object);
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/* denormals will be handled as zero, either with FTZ or DAZ.
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* Since:2 */
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int (*zero_denormals) (void *object, bool enable);
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};
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#define spa_cpu_method(o,method,version,...) \
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({ \
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int _res = -ENOTSUP; \
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struct spa_cpu *_c = o; \
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spa_interface_call_res(&_c->iface, \
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struct spa_cpu_methods, _res, \
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method, version, ##__VA_ARGS__); \
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_res; \
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})
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#define spa_cpu_get_flags(c) spa_cpu_method(c, get_flags, 0)
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#define spa_cpu_force_flags(c,f) spa_cpu_method(c, force_flags, 0, f)
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#define spa_cpu_get_count(c) spa_cpu_method(c, get_count, 0)
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#define spa_cpu_get_max_align(c) spa_cpu_method(c, get_max_align, 0)
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#define spa_cpu_get_vm_type(c) spa_cpu_method(c, get_vm_type, 1)
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#define spa_cpu_zero_denormals(c,e) spa_cpu_method(c, zero_denormals, 2, e)
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/** keys can be given when initializing the cpu handle */
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#define SPA_KEY_CPU_FORCE "cpu.force" /**< force cpu flags */
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#define SPA_KEY_CPU_VM_TYPE "cpu.vm.type" /**< force a VM type */
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#define SPA_KEY_CPU_ZERO_DENORMALS "cpu.zero.denormals" /**< zero denormals */
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/**
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* \}
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*/
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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#endif /* SPA_CPU_H */
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