alsa: force same clock only for pro audio profile

Assume that capture and playback nodes from a device have different
clocks. This enables the adative resampler to match them. A lot of devices
actually have slightly different rates and would work out of the box
with this fix.

Make an exception when the card is configured in the pro audio profile.
Then we force the same clock on all device nodes and avoid resampling
and rate matching. This can still be changed with a session manager
override.
This commit is contained in:
Wim Taymans 2022-06-08 17:03:50 +02:00
parent 47e1f38f03
commit b99c71262e
2 changed files with 10 additions and 1 deletions

View file

@ -381,6 +381,7 @@ static int add_pro_profile(pa_card *impl, uint32_t index)
&try_period_size, &try_buffer_size,
0, NULL, NULL, false))) {
pa_alsa_init_proplist_pcm(NULL, m->output_proplist, m->output_pcm);
pa_proplist_setf(m->output_proplist, "clock.name", "api.alsa.%u", index);
snd_pcm_close(m->output_pcm);
m->output_pcm = NULL;
m->supported = true;
@ -411,6 +412,7 @@ static int add_pro_profile(pa_card *impl, uint32_t index)
&try_period_size, &try_buffer_size,
0, NULL, NULL, false))) {
pa_alsa_init_proplist_pcm(NULL, m->input_proplist, m->input_pcm);
pa_proplist_setf(m->input_proplist, "clock.name", "api.alsa.%u", index);
snd_pcm_close(m->input_pcm);
m->input_pcm = NULL;
m->supported = true;

View file

@ -466,7 +466,9 @@ int spa_alsa_init(struct state *state, const struct spa_dict *info)
}
if (state->clock_name[0] == '\0')
snprintf(state->clock_name, sizeof(state->clock_name),
"api.alsa.%u", state->card_index);
"api.alsa.%s-%u",
state->stream == SND_PCM_STREAM_PLAYBACK ? "p" : "c",
state->card_index);
if (state->stream == SND_PCM_STREAM_PLAYBACK) {
state->is_iec958 = spa_strstartswith(state->props.device, "iec958");
@ -1862,6 +1864,11 @@ static int setup_matching(struct state *state)
state->matching = false;
state->resample = ((uint32_t)state->rate != state->rate_denom) || state->matching;
spa_log_info(state->log, "driver clock:'%s'@%d our clock:'%s'@%d matching:%d resample:%d",
state->position->clock.name, state->rate_denom,
state->clock_name, state->rate,
state->matching, state->resample);
return 0;
}