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audioconvert: fix rounding on arm neon
Add the neon functions to the test
This commit is contained in:
Wim Taymans
parent
1db52856ff
commit
b1b8b0985a
2 changed files with 84 additions and 30 deletions
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@ -26,6 +26,8 @@
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#include <stdio.h>
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#include <math.h>
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#include <arm_neon.h>
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#include "fmt-ops.h"
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void
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@ -289,16 +291,19 @@ conv_f32d_to_s16_2s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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#ifdef __aarch64__
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asm volatile(
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" dup v2.4s, %w[scale]\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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"1:"
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" ld1 { v0.4s }, [%[s0]], #16\n"
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" ld1 { v1.4s }, [%[s1]], #16\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" fcvtzs v0.4s, v0.4s, #31\n"
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" fcvtzs v1.4s, v1.4s, #31\n"
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" sqrshrn v0.4h, v0.4s, #16\n"
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" sqrshrn v1.4h, v1.4s, #16\n"
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" sqadd v0.4s, v0.4s, v2.4s\n"
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" sqadd v1.4s, v1.4s, v2.4s\n"
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" fcvtns v0.4s, v0.4s\n"
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" fcvtns v1.4s, v1.4s\n"
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" sqxtn v0.4h, v0.4s\n"
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" sqxtn v1.4h, v1.4s\n"
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" st2 { v0.h, v1.h }[0], [%[d]], %[stride]\n"
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" st2 { v0.h, v1.h }[1], [%[d]], %[stride]\n"
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" st2 { v0.h, v1.h }[2], [%[d]], %[stride]\n"
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@ -311,29 +316,42 @@ conv_f32d_to_s16_2s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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" ld1 { v0.s }[0], [%[s0]], #4\n"
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" ld1 { v2.s }[0], [%[s1]], #4\n"
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" subs %[remainder], %[remainder], #1\n"
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" fcvtzs v0.4s, v0.4s, #31\n"
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" fcvtzs v1.4s, v1.4s, #31\n"
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" sqrshrn v0.4h, v0.4s, #16\n"
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" sqrshrn v1.4h, v1.4s, #16\n"
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" sqadd v0.4s, v0.4s, v2.4s\n"
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" sqadd v1.4s, v1.4s, v2.4s\n"
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" fcvtns v0.4s, v0.4s\n"
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" fcvtns v1.4s, v1.4s\n"
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" sqxtn v0.4h, v0.4s\n"
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" sqxtn v1.4h, v1.4s\n"
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" st2 { v0.h, v1.h }[0], [%[d]], %[stride]\n"
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" bne 3b\n"
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"4:"
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: [d] "+r" (d), [s0] "+r" (s0), [s1] "+r" (s1), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: [stride] "r" (stride),
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[scale] "r" (15 << 23)
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: "cc", "v0", "v1");
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#else
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float32x4_t pos = vdupq_n_f32(0.4999999f / S16_SCALE);
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float32x4_t neg = vdupq_n_f32(-0.4999999f / S16_SCALE);
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asm volatile(
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" veor q2, q2, q2\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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"1:"
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" vld1.32 { q0 }, [%[s0]]!\n"
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" vld1.32 { q1 }, [%[s1]]!\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vcvt.s32.f32 q1, q1, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vqrshrn.s32 d1, q1, #16\n"
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" vcgt.f32 q3, q0, q2\n"
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" vcgt.f32 q4, q0, q2\n"
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" vbsl q3, %q[pos], %q[neg]\n"
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" vbsl q4, %q[pos], %q[neg]\n"
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" vadd.f32 q0, q0, q3\n"
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" vadd.f32 q1, q1, q4\n"
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" vcvt.s32.f32 q0, q0, #15\n"
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" vcvt.s32.f32 q1, q1, #15\n"
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" vqmovn.s32 d0, q0\n"
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" vqmovn.s32 d1, q1\n"
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" vst2.16 { d0[0], d1[0] }, [%[d]], %[stride]\n"
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" vst2.16 { d0[1], d1[1] }, [%[d]], %[stride]\n"
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" vst2.16 { d0[2], d1[2] }, [%[d]], %[stride]\n"
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@ -346,17 +364,25 @@ conv_f32d_to_s16_2s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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" vld1.32 { d0[0] }, [%[s0]]!\n"
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" vld1.32 { d2[0] }, [%[s1]]!\n"
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" subs %[remainder], %[remainder], #1\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vcvt.s32.f32 q1, q1, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vqrshrn.s32 d1, q1, #16\n"
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" vcgt.f32 q3, q0, q2\n"
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" vcgt.f32 q4, q0, q2\n"
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" vbsl q3, %q[pos], %q[neg]\n"
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" vbsl q4, %q[pos], %q[neg]\n"
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" vadd.f32 q0, q0, q3\n"
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" vadd.f32 q1, q1, q4\n"
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" vcvt.s32.f32 q0, q0, #15\n"
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" vcvt.s32.f32 q1, q1, #15\n"
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" vqmovn.s32 d0, q0\n"
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" vqmovn.s32 d1, q1\n"
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" vst2.16 { d0[0], d1[0] }, [%[d]], %[stride]\n"
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" bne 3b\n"
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"4:"
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: [d] "+r" (d), [s0] "+r" (s0), [s1] "+r" (s1), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: "cc", "q0", "q1");
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: [stride] "r" (stride),
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[pos]"w"(pos),
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[neg]"w"(neg)
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: "cc", "q0", "q1", "q2", "q3", "q4");
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#endif
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}
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@ -372,13 +398,15 @@ conv_f32d_to_s16_1s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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#ifdef __aarch64__
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asm volatile(
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" dup v2.4s, %w[scale]\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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"1:"
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" ld1 { v0.4s }, [%[s]], #16\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" fcvtzs v0.4s, v0.4s, #31\n"
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" sqrshrn v0.4h, v0.4s, #16\n"
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" sqadd v0.4s, v0.4s, v2.4s\n"
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" fcvtns v0.4s, v0.4s\n"
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" sqxtn v0.4h, v0.4s\n"
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" st1 { v0.h }[0], [%[d]], %[stride]\n"
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" st1 { v0.h }[1], [%[d]], %[stride]\n"
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" st1 { v0.h }[2], [%[d]], %[stride]\n"
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@ -390,24 +418,33 @@ conv_f32d_to_s16_1s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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"3:"
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" ld1 { v0.s }[0], [%[s]], #4\n"
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" subs %[remainder], %[remainder], #1\n"
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" fcvtzs v0.4s, v0.4s, #31\n"
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" sqrshrn v0.4h, v0.4s, #16\n"
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" sqadd v0.4s, v0.4s, v2.4s\n"
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" fcvtns v0.4s, v0.4s\n"
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" sqxtn v0.4h, v0.4s\n"
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" st1 { v0.h }[0], [%[d]], %[stride]\n"
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" bne 3b\n"
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"4:"
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: [d] "+r" (d), [s] "+r" (s), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: [stride] "r" (stride),
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[scale] "r" (15 << 23)
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: "cc", "v0");
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#else
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float32x4_t pos = vdupq_n_f32(0.4999999f / S16_SCALE);
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float32x4_t neg = vdupq_n_f32(-0.4999999f / S16_SCALE);
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asm volatile(
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" veor q1, q1, q1\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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"1:"
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" vld1.32 { q0 }, [%[s]]!\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vcgt.f32 q2, q0, q1\n"
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" vbsl q2, %q[pos], %q[neg]\n"
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" vadd.f32 q0, q0, q2\n"
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" vcvt.s32.f32 q0, q0, #15\n"
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" vqmovn.s32 d0, q0\n"
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" vst1.16 { d0[0] }, [%[d]], %[stride]\n"
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" vst1.16 { d0[1] }, [%[d]], %[stride]\n"
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" vst1.16 { d0[2] }, [%[d]], %[stride]\n"
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@ -419,15 +456,20 @@ conv_f32d_to_s16_1s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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"3:"
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" vld1.32 { d0[0] }, [%[s]]!\n"
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" subs %[remainder], %[remainder], #1\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vcgt.f32 q2, q0, q1\n"
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" vbsl q2, %q[pos], %q[neg]\n"
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" vadd.f32 q0, q0, q2\n"
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" vcvt.s32.f32 q0, q0, #15\n"
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" vqmovn.s32 d0, q0\n"
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" vst1.16 { d0[0] }, [%[d]], %[stride]\n"
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" bne 3b\n"
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"4:"
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: [d] "+r" (d), [s] "+r" (s), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: "cc", "q0");
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: [stride] "r" (stride),
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[pos]"w"(pos),
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[neg]"w"(neg)
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: "cc", "q0", "q1", "q2");
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#endif
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}
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@ -242,6 +242,12 @@ static void test_f32_s16(void)
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false, true, conv_f32d_to_s16_avx2);
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}
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#endif
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#if defined(HAVE_NEON)
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if (cpu_flags & SPA_CPU_FLAG_NEON) {
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run_test("test_f32d_s16_neon", in, sizeof(in[0]), out, sizeof(out[0]), SPA_N_ELEMENTS(out),
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false, true, conv_f32d_to_s16_neon);
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}
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#endif
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}
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static void test_s16_f32(void)
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@ -269,6 +275,12 @@ static void test_s16_f32(void)
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true, false, conv_s16_to_f32d_avx2);
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}
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#endif
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#if defined(HAVE_NEON)
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if (cpu_flags & SPA_CPU_FLAG_NEON) {
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run_test("test_s16_f32d_neon", in, sizeof(in[0]), out, sizeof(out[0]), SPA_N_ELEMENTS(out),
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true, false, conv_s16_to_f32d_neon);
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}
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#endif
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}
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static void test_f32_u32(void)
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