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fmt-ops: add RVV optimizations for f32d_s16
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5 changed files with 54 additions and 0 deletions
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@ -137,6 +137,7 @@ static void test_f32_s16(void)
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if (cpu_flags & SPA_CPU_FLAG_RISCV_V) {
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run_test("test_f32_s16", "rvv", true, true, conv_f32_to_s16_rvv);
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run_test("test_f32d_s16d", "rvv", false, false, conv_f32d_to_s16d_rvv);
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run_test("test_f32d_s16", "rvv", false, true, conv_f32d_to_s16_rvv);
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}
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#endif
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run_test("test_f32_s16d", "c", true, false, conv_f32_to_s16d_c);
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@ -60,4 +60,53 @@ conv_f32d_to_s16d_rvv(struct convert *conv, void * SPA_RESTRICT dst[], const voi
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f32_to_s16(conv, dst[i], src[i], n_samples);
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}
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}
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static void
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f32d_to_s16(void *data, void * SPA_RESTRICT dst, const void * SPA_RESTRICT src[],
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uint32_t n_channels, uint32_t n_samples)
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{
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const float *s = src[0];
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uint32_t stride = n_channels << 1;
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asm __volatile__ (
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".option arch, +v \n\t"
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"li t0, 1191182336 \n\t"
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"fmv.w.x fa5, t0 \n\t"
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"1: \n\t"
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"vsetvli t0, %[n_samples], e32, m8, ta, ma \n\t"
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"vle32.v v8, (%[s]) \n\t"
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"sub %[n_samples], %[n_samples], t0 \n\t"
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"vfmul.vf v8, v8, fa5 \n\t"
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"vsetvli zero, zero, e16, m4, ta, ma \n\t"
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"vfncvt.x.f.w v8, v8 \n\t"
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"slli t2, t0, 1 \n\t"
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"vsse16.v v8, (%[dst]), %[stride] \n\t"
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"add %[s], %[s], t2 \n\t"
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"add %[s], %[s], t2 \n\t"
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"mul t0, t0, %[stride] \n\t"
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"add %[dst], %[dst], t0 \n\t"
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"bnez %[n_samples], 1b \n\t"
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: [n_samples] "+r" (n_samples),
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[s] "+r" (s),
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[dst] "+r" (dst)
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: [stride] "r" (stride)
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: "cc", "memory"
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);
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}
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void
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conv_f32d_to_s16_rvv(struct convert *conv, void * SPA_RESTRICT dst[], const void * SPA_RESTRICT src[],
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uint32_t n_samples)
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{
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if (n_samples <= 4) {
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conv_f32d_to_s16_c(conv, dst, src, n_samples);
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return;
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}
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int16_t *d = dst[0];
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uint32_t i = 0, n_channels = conv->n_channels;
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for(i = 0; i < n_channels; i++)
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f32d_to_s16(conv, &d[i], &src[i], n_channels, n_samples);
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}
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#endif
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@ -180,6 +180,7 @@ static struct conv_info conv_table[] =
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#if defined (HAVE_RVV)
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MAKE(F32, S16, 0, conv_f32_to_s16_rvv, SPA_CPU_FLAG_RISCV_V),
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MAKE(F32P, S16P, 0, conv_f32d_to_s16d_rvv, SPA_CPU_FLAG_RISCV_V),
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MAKE(F32P, S16, 0, conv_f32d_to_s16_rvv, SPA_CPU_FLAG_RISCV_V),
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#endif
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MAKE(F32, S16, 0, conv_f32_to_s16_c),
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@ -443,6 +443,7 @@ DEFINE_FUNCTION(f32d_to_s16, neon);
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#if defined(HAVE_RVV)
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DEFINE_FUNCTION(f32_to_s16, rvv);
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DEFINE_FUNCTION(f32d_to_s16d, rvv);
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DEFINE_FUNCTION(f32d_to_s16, rvv);
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#endif
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#if defined(HAVE_SSE2)
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DEFINE_FUNCTION(s16_to_f32d_2, sse2);
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@ -234,6 +234,8 @@ static void test_f32_s16(void)
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true, true, conv_f32_to_s16_rvv);
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run_test("test_f32d_s16d_rvv", in, sizeof(in[0]), out, sizeof(out[0]), SPA_N_ELEMENTS(out),
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false, false, conv_f32d_to_s16d_rvv);
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run_test("test_f32d_s16_rvv", in, sizeof(in[0]), out, sizeof(out[0]), SPA_N_ELEMENTS(out),
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false, true, conv_f32d_to_s16_rvv);
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}
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#endif
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}
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