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fmt-ops: add RVV optimizations for f32d_s16d
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parent
9348ad8115
commit
852de6c35c
5 changed files with 50 additions and 25 deletions
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@ -136,6 +136,7 @@ static void test_f32_s16(void)
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#if defined (HAVE_RVV)
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#if defined (HAVE_RVV)
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if (cpu_flags & SPA_CPU_FLAG_RISCV_V) {
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if (cpu_flags & SPA_CPU_FLAG_RISCV_V) {
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run_test("test_f32_s16", "rvv", true, true, conv_f32_to_s16_rvv);
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run_test("test_f32_s16", "rvv", true, true, conv_f32_to_s16_rvv);
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run_test("test_f32d_s16d", "rvv", false, false, conv_f32d_to_s16d_rvv);
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}
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}
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#endif
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#endif
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run_test("test_f32_s16d", "c", true, false, conv_f32_to_s16d_c);
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run_test("test_f32_s16d", "c", true, false, conv_f32_to_s16d_c);
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@ -5,6 +5,35 @@
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#include "fmt-ops.h"
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#include "fmt-ops.h"
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#if HAVE_RVV
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#if HAVE_RVV
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void
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f32_to_s16(struct convert *conv, void * SPA_RESTRICT dst[], const void * SPA_RESTRICT src,
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uint32_t n_samples)
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{
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asm __volatile__ (
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".option arch, +v \n\t"
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"li t0, 1191182336 \n\t"
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"fmv.w.x fa5, t0 \n\t"
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"1: \n\t"
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"vsetvli t0, %[n_samples], e32, m8, ta, ma \n\t"
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"vle32.v v8, (%[src]) \n\t"
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"sub %[n_samples], %[n_samples], t0 \n\t"
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"vfmul.vf v8, v8, fa5 \n\t"
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"vsetvli zero, zero, e16, m4, ta, ma \n\t"
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"vfncvt.x.f.w v8, v8 \n\t"
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"slli t0, t0, 1 \n\t"
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"vse16.v v8, (%[dst]) \n\t"
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"add %[src], %[src], t0 \n\t"
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"add %[dst], %[dst], t0 \n\t"
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"add %[src], %[src], t0 \n\t"
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"bnez %[n_samples], 1b \n\t"
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: [n_samples] "+r" (n_samples),
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[src] "+r" (src),
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[dst] "+r" (dst)
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:
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: "cc", "memory"
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);
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}
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void
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void
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conv_f32_to_s16_rvv(struct convert *conv, void * SPA_RESTRICT dst[], const void * SPA_RESTRICT src[],
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conv_f32_to_s16_rvv(struct convert *conv, void * SPA_RESTRICT dst[], const void * SPA_RESTRICT src[],
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uint32_t n_samples)
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uint32_t n_samples)
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@ -14,30 +43,21 @@ conv_f32_to_s16_rvv(struct convert *conv, void * SPA_RESTRICT dst[], const void
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return;
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return;
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}
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}
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__asm__ __volatile__ (
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f32_to_s16(conv, *dst, *src, n_samples * conv -> n_channels);
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".option arch, +v \n\t"
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}
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"ld a1, (a1) \n\t"
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"ld a2, (a2) \n\t"
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void
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"lwu a0, 16(a0) \n\t"
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conv_f32d_to_s16d_rvv(struct convert *conv, void * SPA_RESTRICT dst[], const void * SPA_RESTRICT src[],
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"li t0, 1191182336 \n\t"
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uint32_t n_samples)
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"mul a0, a0, a3 \n\t"
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{
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"fmv.w.x fa5, t0 \n\t"
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if (n_samples <= 4) {
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"1: \n\t"
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conv_f32d_to_s16d_c(conv, dst, src, n_samples);
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"vsetvli t0, a0, e32, m8, ta, ma \n\t"
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return;
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"vle32.v v8, (a2) \n\t"
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}
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"sub a0, a0, t0 \n\t"
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"vfmul.vf v8, v8, fa5 \n\t"
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uint32_t i = 0, n_channels = conv->n_channels;
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"vsetvli zero, zero, e16, m4, ta, ma \n\t"
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for(i = 0; i < n_channels; i++) {
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"vfncvt.x.f.w v8, v8 \n\t"
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f32_to_s16(conv, dst[i], src[i], n_samples);
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"slli t0, t0, 1 \n\t"
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}
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"vse16.v v8, (a1) \n\t"
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"add a2, a2, t0 \n\t"
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"add a1, a1, t0 \n\t"
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"add a2, a2, t0 \n\t"
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"bnez a0, 1b \n\t"
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:
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:
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: "cc", "memory"
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);
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}
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}
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#endif
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#endif
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@ -179,6 +179,7 @@ static struct conv_info conv_table[] =
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#endif
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#endif
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#if defined (HAVE_RVV)
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#if defined (HAVE_RVV)
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MAKE(F32, S16, 0, conv_f32_to_s16_rvv, SPA_CPU_FLAG_RISCV_V),
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MAKE(F32, S16, 0, conv_f32_to_s16_rvv, SPA_CPU_FLAG_RISCV_V),
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MAKE(F32P, S16P, 0, conv_f32d_to_s16d_rvv, SPA_CPU_FLAG_RISCV_V),
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#endif
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#endif
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MAKE(F32, S16, 0, conv_f32_to_s16_c),
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MAKE(F32, S16, 0, conv_f32_to_s16_c),
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@ -442,6 +442,7 @@ DEFINE_FUNCTION(f32d_to_s16, neon);
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#endif
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#endif
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#if defined(HAVE_RVV)
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#if defined(HAVE_RVV)
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DEFINE_FUNCTION(f32_to_s16, rvv);
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DEFINE_FUNCTION(f32_to_s16, rvv);
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DEFINE_FUNCTION(f32d_to_s16d, rvv);
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#endif
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#endif
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#if defined(HAVE_SSE2)
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#if defined(HAVE_SSE2)
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DEFINE_FUNCTION(s16_to_f32d_2, sse2);
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DEFINE_FUNCTION(s16_to_f32d_2, sse2);
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@ -232,6 +232,8 @@ static void test_f32_s16(void)
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if (cpu_flags & SPA_CPU_FLAG_RISCV_V) {
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if (cpu_flags & SPA_CPU_FLAG_RISCV_V) {
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run_test("test_f32_s16_rvv", in, sizeof(in[0]), out, sizeof(out[0]), SPA_N_ELEMENTS(out),
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run_test("test_f32_s16_rvv", in, sizeof(in[0]), out, sizeof(out[0]), SPA_N_ELEMENTS(out),
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true, true, conv_f32_to_s16_rvv);
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true, true, conv_f32_to_s16_rvv);
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run_test("test_f32d_s16d_rvv", in, sizeof(in[0]), out, sizeof(out[0]), SPA_N_ELEMENTS(out),
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false, false, conv_f32d_to_s16d_rvv);
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}
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}
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#endif
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#endif
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}
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}
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