spa/support: implement RISCV V CPU detection

meson.build

@@ -177,6 +177,20 @@ elif cc.has_argument('-mfpu=neon')
   endif
 endif
 
+have_rvv = false
+if host_machine.cpu_family() == 'riscv64'
+  if cc.compiles('''
+      int main() {
+          __asm__ __volatile__ (
+            ".option arch, +v\nvsetivli zero, 0, e8, m1, ta, ma"
+          );
+      }
+    ''',
+    name : 'riscv64 V Support')
+      have_rvv = true
+  endif
+endif
+
 libatomic = cc.find_library('atomic', required : false)
 
 test_8_byte_atomic = '''
@@ -237,6 +251,7 @@ if host_machine.endian() == 'big'
 endif
 
 check_headers = [
+  ['sys/auxv.h', 'HAVE_SYS_AUXV_H'],
   ['sys/mount.h', 'HAVE_SYS_MOUNT_H'],
   ['sys/param.h', 'HAVE_SYS_PARAM_H'],
   ['sys/random.h', 'HAVE_SYS_RANDOM_H'],

spa/include/spa/support/cpu.h

@@ -68,6 +68,9 @@ struct spa_cpu { struct spa_interface iface; };
 #define SPA_CPU_FLAG_NEON		(1 << 5)
 #define SPA_CPU_FLAG_ARMV8		(1 << 6)
 
+/* RISCV specific */
+#define SPA_CPU_FLAG_RISCV_V		(1 << 0)
+
 #define SPA_CPU_FORCE_AUTODETECT	((uint32_t)-1)
 
 #define SPA_CPU_VM_NONE			(0)

spa/plugins/support/cpu-riscv.c

@@ -0,0 +1,29 @@
+/* Spa */
+/* SPDX-FileCopyrightText: Copyright (c) 2023 Institue of Software Chinese Academy of Sciences (ISCAS). */
+/* SPDX-License-Identifier: MIT */
+
+#ifdef HAVE_SYS_AUXV_H
+#include <sys/auxv.h>
+#define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
+#endif
+
+static int
+riscv_init(struct impl *impl)
+{
+	uint32_t flags = 0;
+
+#ifdef HAVE_SYS_AUXV_H
+	const unsigned long hwcap = getauxval(AT_HWCAP);
+	if (hwcap & HWCAP_RV('V'))
+		flags |= SPA_CPU_FLAG_RISCV_V;
+#endif
+
+	impl->flags = flags;
+
+	return 0;
+}
+
+static int riscv_zero_denormals(void *object, bool enable)
+{
+	return 0;
+}

spa/plugins/support/cpu.c

@@ -64,6 +64,10 @@ static char *spa_cpu_read_file(const char *name, char *buffer, size_t len)
 #include "cpu-arm.c"
 #define init(t)	arm_init(t)
 #define impl_cpu_zero_denormals arm_zero_denormals
+# elif defined (__riscv)
+#include "cpu-riscv.c"
+#define init(t)	riscv_init(t)
+#define impl_cpu_zero_denormals riscv_zero_denormals
 # else
 #define init(t)
 #define impl_cpu_zero_denormals NULL

spa/plugins/support/meson.build

@@ -14,9 +14,17 @@ if have_sse
   simd_cargs += [sse_args, '-DHAVE_SSE']
 endif
 
+header_cargs = []
+
+if host_machine.cpu_family() == 'riscv64'
+  if cdata.get('HAVE_SYS_AUXV_H')
+    header_cargs += ['-DHAVE_SYS_AUXV_H']
+  endif
+endif
+
 spa_support_lib = shared_library('spa-support',
   spa_support_sources,
-  c_args : [ simd_cargs ],
+  c_args : [ simd_cargs, header_cargs ],
   dependencies : [ spa_dep, pthread_lib, epoll_shim_dep, mathlib ],
   install : true,
   install_dir : spa_plugindir / 'support')