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spa/support: implement RISCV V CPU detection

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sunyuechi 2024-09-16 23:13:16 +08:00 • committed by Wim Taymans
parent e2991f6398
commit 8166b9c580
5 changed files with 60 additions and 1 deletions
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10
spa/plugins/support/meson.build
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@ -14,9 +14,17 @@ if have_sse
simd_cargs += [sse_args, '-DHAVE_SSE']
endif
header_cargs = []
if host_machine.cpu_family() == 'riscv64'
if cdata.get('HAVE_SYS_AUXV_H')
header_cargs += ['-DHAVE_SYS_AUXV_H']
endif
endif
spa_support_lib = shared_library('spa-support',
spa_support_sources,
c_args : [ simd_cargs ],
c_args : [ simd_cargs, header_cargs ],
dependencies : [ spa_dep, pthread_lib, epoll_shim_dep, mathlib ],
install : true,
install_dir : spa_plugindir / 'support')