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spa/support: implement RISCV V CPU detection

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sunyuechi 2024-09-16 23:13:16 +08:00 • committed by Wim Taymans
parent e2991f6398
commit 8166b9c580
5 changed files with 60 additions and 1 deletions
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29
spa/plugins/support/cpu-riscv.c Normal file
View file

@ -0,0 +1,29 @@
/* Spa */
/* SPDX-FileCopyrightText: Copyright (c) 2023 Institue of Software Chinese Academy of Sciences (ISCAS). */
/* SPDX-License-Identifier: MIT */
#ifdef HAVE_SYS_AUXV_H
#include <sys/auxv.h>
#define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
#endif
static int
riscv_init(struct impl *impl)
{
uint32_t flags = 0;
#ifdef HAVE_SYS_AUXV_H
const unsigned long hwcap = getauxval(AT_HWCAP);
if (hwcap & HWCAP_RV('V'))
flags |= SPA_CPU_FLAG_RISCV_V;
#endif
impl->flags = flags;
return 0;
}
static int riscv_zero_denormals(void *object, bool enable)
{
return 0;
}

4
spa/plugins/support/cpu.c
View file

@ -64,6 +64,10 @@ static char *spa_cpu_read_file(const char *name, char *buffer, size_t len)
#include "cpu-arm.c"
#define init(t) arm_init(t)
#define impl_cpu_zero_denormals arm_zero_denormals
# elif defined (__riscv)
#include "cpu-riscv.c"
#define init(t) riscv_init(t)
#define impl_cpu_zero_denormals riscv_zero_denormals
# else
#define init(t)
#define impl_cpu_zero_denormals NULL

10
spa/plugins/support/meson.build
View file

@ -14,9 +14,17 @@ if have_sse
simd_cargs += [sse_args, '-DHAVE_SSE']
endif
header_cargs = []
if host_machine.cpu_family() == 'riscv64'
if cdata.get('HAVE_SYS_AUXV_H')
header_cargs += ['-DHAVE_SYS_AUXV_H']
endif
endif
spa_support_lib = shared_library('spa-support',
spa_support_sources,
c_args : [ simd_cargs ],
c_args : [ simd_cargs, header_cargs ],
dependencies : [ spa_dep, pthread_lib, epoll_shim_dep, mathlib ],
install : true,
install_dir : spa_plugindir / 'support')