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Channel mixer: Remove channelmix_f32_2_4_sse
It does not have PSD upmixing implemented and does not allow to disable the simple upmixing algorithm either. Fixes #2438.
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a1d4b41c34
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3 changed files with 0 additions and 71 deletions
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@ -70,73 +70,6 @@ void channelmix_copy_sse(struct channelmix *mix, void * SPA_RESTRICT dst[],
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}
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}
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}
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}
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void
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channelmix_f32_2_4_sse(struct channelmix *mix, void * SPA_RESTRICT dst[],
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const void * SPA_RESTRICT src[], uint32_t n_samples)
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{
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uint32_t i, n, unrolled, n_dst = mix->dst_chan;
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float **d = (float **)dst;
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const float **s = (const float **)src;
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const float m00 = mix->matrix[0][0];
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const float m11 = mix->matrix[1][1];
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__m128 in;
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const float *sFL = s[0], *sFR = s[1];
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float *dFL = d[0], *dFR = d[1], *dRL = d[2], *dRR = d[3];
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if (SPA_IS_ALIGNED(sFL, 16) &&
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SPA_IS_ALIGNED(sFR, 16) &&
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SPA_IS_ALIGNED(dFL, 16) &&
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SPA_IS_ALIGNED(dFR, 16) &&
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SPA_IS_ALIGNED(dRL, 16) &&
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SPA_IS_ALIGNED(dRR, 16))
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unrolled = n_samples & ~3;
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else
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unrolled = 0;
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if (SPA_FLAG_IS_SET(mix->flags, CHANNELMIX_FLAG_ZERO)) {
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for (i = 0; i < n_dst; i++)
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memset(d[i], 0, n_samples * sizeof(float));
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}
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else if (m00 == 1.0f && m11 == 1.0f) {
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for(n = 0; n < unrolled; n += 4) {
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in = _mm_load_ps(&sFL[n]);
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_mm_store_ps(&dFL[n], in);
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_mm_store_ps(&dRL[n], in);
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in = _mm_load_ps(&sFR[n]);
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_mm_store_ps(&dFR[n], in);
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_mm_store_ps(&dRR[n], in);
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}
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for(; n < n_samples; n++) {
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in = _mm_load_ss(&sFL[n]);
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_mm_store_ss(&dFL[n], in);
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_mm_store_ss(&dRL[n], in);
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in = _mm_load_ss(&sFR[n]);
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_mm_store_ss(&dFR[n], in);
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_mm_store_ss(&dRR[n], in);
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}
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}
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else {
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const __m128 v0 = _mm_set1_ps(m00);
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const __m128 v1 = _mm_set1_ps(m11);
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for(n = 0; n < unrolled; n += 4) {
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in = _mm_mul_ps(_mm_load_ps(&sFL[n]), v0);
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_mm_store_ps(&dFL[n], in);
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_mm_store_ps(&dRL[n], in);
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in = _mm_mul_ps(_mm_load_ps(&sFR[n]), v1);
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_mm_store_ps(&dFR[n], in);
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_mm_store_ps(&dRR[n], in);
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}
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for(; n < n_samples; n++) {
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in = _mm_mul_ss(_mm_load_ss(&sFL[n]), v0);
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_mm_store_ss(&dFL[n], in);
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_mm_store_ss(&dRL[n], in);
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in = _mm_mul_ss(_mm_load_ss(&sFR[n]), v1);
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_mm_store_ss(&dFR[n], in);
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_mm_store_ss(&dRR[n], in);
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}
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}
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}
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/* FL+FR+FC+LFE+SL+SR -> FL+FR */
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/* FL+FR+FC+LFE+SL+SR -> FL+FR */
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void
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void
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channelmix_f32_5p1_2_sse(struct channelmix *mix, void * SPA_RESTRICT dst[],
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channelmix_f32_5p1_2_sse(struct channelmix *mix, void * SPA_RESTRICT dst[],
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@ -79,9 +79,6 @@ static const struct channelmix_info {
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{ 2, MASK_STEREO, 1, MASK_MONO, channelmix_f32_2_1_c, 0, "f32_2_1_c" },
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{ 2, MASK_STEREO, 1, MASK_MONO, channelmix_f32_2_1_c, 0, "f32_2_1_c" },
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{ 4, MASK_QUAD, 1, MASK_MONO, channelmix_f32_4_1_c, 0, "f32_4_1_c" },
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{ 4, MASK_QUAD, 1, MASK_MONO, channelmix_f32_4_1_c, 0, "f32_4_1_c" },
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{ 4, MASK_3_1, 1, MASK_MONO, channelmix_f32_4_1_c, 0, "f32_4_1_c" },
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{ 4, MASK_3_1, 1, MASK_MONO, channelmix_f32_4_1_c, 0, "f32_4_1_c" },
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#if defined (HAVE_SSE)
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{ 2, MASK_STEREO, 4, MASK_QUAD, channelmix_f32_2_4_sse, SPA_CPU_FLAG_SSE, "f32_2_4_sse" },
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#endif
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{ 2, MASK_STEREO, 4, MASK_QUAD, channelmix_f32_2_4_c, 0, "f32_2_4_c" },
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{ 2, MASK_STEREO, 4, MASK_QUAD, channelmix_f32_2_4_c, 0, "f32_2_4_c" },
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{ 2, MASK_STEREO, 4, MASK_3_1, channelmix_f32_2_3p1_c, 0, "f32_2_3p1_c" },
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{ 2, MASK_STEREO, 4, MASK_3_1, channelmix_f32_2_3p1_c, 0, "f32_2_3p1_c" },
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{ 2, MASK_STEREO, 6, MASK_5_1, channelmix_f32_2_5p1_c, 0, "f32_2_5p1_c" },
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{ 2, MASK_STEREO, 6, MASK_5_1, channelmix_f32_2_5p1_c, 0, "f32_2_5p1_c" },
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@ -151,7 +151,6 @@ DEFINE_FUNCTION(f32_7p1_4, c);
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#if defined (HAVE_SSE)
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#if defined (HAVE_SSE)
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DEFINE_FUNCTION(copy, sse);
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DEFINE_FUNCTION(copy, sse);
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DEFINE_FUNCTION(f32_2_4, sse);
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DEFINE_FUNCTION(f32_5p1_2, sse);
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DEFINE_FUNCTION(f32_5p1_2, sse);
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DEFINE_FUNCTION(f32_5p1_3p1, sse);
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DEFINE_FUNCTION(f32_5p1_3p1, sse);
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DEFINE_FUNCTION(f32_5p1_4, sse);
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DEFINE_FUNCTION(f32_5p1_4, sse);
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