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synced 2025-11-02 09:01:50 -05:00
fmt-ops: add arm32 optimizations
This commit is contained in:
Wim Taymans
parent
a81e269a7e
commit
167460a9bc
1 changed files with 128 additions and 29 deletions
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@ -34,12 +34,11 @@ conv_s16_to_f32d_2s_neon(void *data, void * SPA_RESTRICT dst[], const void * SPA
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{
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{
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const int16_t *s = src;
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const int16_t *s = src;
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float *d0 = dst[0], *d1 = dst[1];
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float *d0 = dst[0], *d1 = dst[1];
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#ifdef __aarch64__
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uint32_t stride = n_channels << 1;
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uint32_t stride = n_channels << 1;
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unsigned int remainder = n_samples & 3;
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unsigned int remainder = n_samples & 3;
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n_samples -= remainder;
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n_samples -= remainder;
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#ifdef __aarch64__
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asm volatile(
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asm volatile(
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" cmp %[n_samples], #0\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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" beq 2f\n"
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@ -75,12 +74,40 @@ conv_s16_to_f32d_2s_neon(void *data, void * SPA_RESTRICT dst[], const void * SPA
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: [stride] "r" (stride)
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: [stride] "r" (stride)
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: "cc", "v0", "v1", "v2", "v3");
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: "cc", "v0", "v1", "v2", "v3");
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#else
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#else
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uint32_t n;
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asm volatile(
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for(n = 0; n < n_samples; n++) {
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" cmp %[n_samples], #0\n"
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*d0++ = S16_TO_F32(s[0]);
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" beq 2f\n"
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*d1++ = S16_TO_F32(s[1]);
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"1:"
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s += n_channels;
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" vld2.16 { d0[0], d1[0] }, [%[s]], %[stride]\n"
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}
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" vld2.16 { d0[1], d1[1] }, [%[s]], %[stride]\n"
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" vld2.16 { d0[2], d1[2] }, [%[s]], %[stride]\n"
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" vld2.16 { d0[3], d1[3] }, [%[s]], %[stride]\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" vmovl.s16 q1, d1\n"
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" vmovl.s16 q0, d0\n"
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" vcvt.f32.s32 q0, q0, #15\n"
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" vcvt.f32.s32 q1, q1, #15\n"
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" vst1.32 { q0 }, [%[d0]]!\n"
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" vst1.32 { q1 }, [%[d1]]!\n"
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" bne 1b\n"
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"2:"
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" cmp %[remainder], #0\n"
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" beq 4f\n"
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"3:"
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" vld2.16 { d0[0], d1[0] }, [%[s]], %[stride]\n"
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" subs %[remainder], %[remainder], #1\n"
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" vmovl.s16 q1, d1\n"
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" vmovl.s16 q0, d0\n"
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" vcvt.f32.s32 q0, q0, #15\n"
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" vcvt.f32.s32 q1, q1, #15\n"
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" vst1.32 { d0[0] }, [%[d0]]!\n"
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" vst1.32 { d1[0] }, [%[d1]]!\n"
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" bne 3b\n"
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"4:"
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: [d0] "+r" (d0), [d1] "+r" (d1), [s] "+r" (s), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: "cc", "q0", "q1");
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#endif
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#endif
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}
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}
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@ -90,11 +117,11 @@ conv_s16_to_f32d_1s_neon(void *data, void * SPA_RESTRICT dst[], const void * SPA
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{
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{
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const int16_t *s = src;
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const int16_t *s = src;
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float *d = dst[0];
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float *d = dst[0];
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#ifdef __aarch64__
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uint32_t stride = n_channels << 1;
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uint32_t stride = n_channels << 1;
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uint32_t remainder = n_samples & 3;
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uint32_t remainder = n_samples & 3;
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n_samples -= remainder;
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n_samples -= remainder;
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#ifdef __aarch64__
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asm volatile(
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asm volatile(
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" cmp %[n_samples], #0\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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" beq 2f\n"
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@ -124,11 +151,34 @@ conv_s16_to_f32d_1s_neon(void *data, void * SPA_RESTRICT dst[], const void * SPA
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: [stride] "r" (stride)
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: [stride] "r" (stride)
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: "cc", "v0", "v1");
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: "cc", "v0", "v1");
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#else
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#else
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uint32_t n;
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asm volatile(
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for(n = 0; n < n_samples; n++) {
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" cmp %[n_samples], #0\n"
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*d++ = S16_TO_F32(s[0]);
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" beq 2f\n"
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s += n_channels;
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"1:"
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}
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" vld1.16 { d0[0] }, [%[s]], %[stride]\n"
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" vld1.16 { d0[1] }, [%[s]], %[stride]\n"
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" vld1.16 { d0[2] }, [%[s]], %[stride]\n"
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" vld1.16 { d0[3] }, [%[s]], %[stride]\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" vmovl.s16 q0, d0\n"
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" vcvt.f32.s32 q0, q0, #15\n"
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" vst1.32 { q0 }, [%[d]]!\n"
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" bne 1b\n"
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"2:"
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" cmp %[remainder], #0\n"
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" beq 4f\n"
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"3:"
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" vld1.16 { d0[0] }, [%[s]], %[stride]\n"
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" subs %[remainder], %[remainder], #1\n"
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" vmovl.s16 q0, d0\n"
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" vcvt.f32.s32 q0, q0, #15\n"
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" vst1.32 { d0[0] }, [%[d]]!\n"
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" bne 3b\n"
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"4:"
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: [d] "+r" (d), [s] "+r" (s), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: "cc", "q0");
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#endif
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#endif
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}
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}
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@ -151,12 +201,11 @@ conv_f32d_to_s16_2s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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{
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{
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const float *s0 = src[0], *s1 = src[1];
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const float *s0 = src[0], *s1 = src[1];
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int16_t *d = dst;
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int16_t *d = dst;
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#ifdef __aarch64__
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uint32_t stride = n_channels << 1;
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uint32_t stride = n_channels << 1;
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uint32_t remainder = n_samples & 3;
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uint32_t remainder = n_samples & 3;
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n_samples -= remainder;
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n_samples -= remainder;
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#ifdef __aarch64__
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asm volatile(
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asm volatile(
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" cmp %[n_samples], #0\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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" beq 2f\n"
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@ -192,12 +241,40 @@ conv_f32d_to_s16_2s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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: [stride] "r" (stride)
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: [stride] "r" (stride)
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: "cc", "v0", "v1");
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: "cc", "v0", "v1");
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#else
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#else
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uint32_t n;
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asm volatile(
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for(n = 0; n < n_samples; n++) {
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" cmp %[n_samples], #0\n"
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d[0] = F32_TO_S16(s0[n]);
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" beq 2f\n"
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d[1] = F32_TO_S16(s1[n]);
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"1:"
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d += n_channels;
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" vld1.32 { q0 }, [%[s0]]!\n"
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}
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" vld1.32 { q1 }, [%[s1]]!\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vcvt.s32.f32 q1, q1, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vqrshrn.s32 d1, q1, #16\n"
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" vst2.16 { d0[0], d1[0] }, [%[d]], %[stride]\n"
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" vst2.16 { d0[1], d1[1] }, [%[d]], %[stride]\n"
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" vst2.16 { d0[2], d1[2] }, [%[d]], %[stride]\n"
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" vst2.16 { d0[3], d1[3] }, [%[d]], %[stride]\n"
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" bne 1b\n"
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"2:"
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" cmp %[remainder], #0\n"
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" beq 4f\n"
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"3:"
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" vld1.32 { d0[0] }, [%[s0]]!\n"
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" vld1.32 { d2[0] }, [%[s1]]!\n"
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" subs %[remainder], %[remainder], #1\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vcvt.s32.f32 q1, q1, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vqrshrn.s32 d1, q1, #16\n"
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" vst2.16 { d0[0], d1[0] }, [%[d]], %[stride]\n"
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" bne 3b\n"
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"4:"
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: [d] "+r" (d), [s0] "+r" (s0), [s1] "+r" (s1), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: "cc", "q0", "q1");
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#endif
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#endif
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}
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}
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@ -207,12 +284,11 @@ conv_f32d_to_s16_1s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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{
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{
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const float *s = src[0];
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const float *s = src[0];
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int16_t *d = dst;
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int16_t *d = dst;
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#ifdef __aarch64__
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uint32_t stride = n_channels << 1;
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uint32_t stride = n_channels << 1;
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uint32_t remainder = n_samples & 3;
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uint32_t remainder = n_samples & 3;
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n_samples -= remainder;
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n_samples -= remainder;
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#ifdef __aarch64__
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asm volatile(
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asm volatile(
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" cmp %[n_samples], #0\n"
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" cmp %[n_samples], #0\n"
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" beq 2f\n"
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" beq 2f\n"
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@ -242,11 +318,34 @@ conv_f32d_to_s16_1s_neon(void *data, void * SPA_RESTRICT dst, const void * SPA_R
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: [stride] "r" (stride)
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: [stride] "r" (stride)
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: "cc", "v0");
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: "cc", "v0");
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#else
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#else
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uint32_t n;
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asm volatile(
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for(n = 0; n < n_samples; n++) {
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" cmp %[n_samples], #0\n"
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*d = F32_TO_S16(s[n]);
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" beq 2f\n"
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d += n_channels;
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"1:"
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}
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" vld1.32 { q0 }, [%[s]]!\n"
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" subs %[n_samples], %[n_samples], #4\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vst1.16 { d0[0] }, [%[d]], %[stride]\n"
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" vst1.16 { d0[1] }, [%[d]], %[stride]\n"
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" vst1.16 { d0[2] }, [%[d]], %[stride]\n"
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" vst1.16 { d0[3] }, [%[d]], %[stride]\n"
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" bne 1b\n"
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"2:"
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" cmp %[remainder], #0\n"
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" beq 4f\n"
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"3:"
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" vld1.32 { d0[0] }, [%[s]]!\n"
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" subs %[remainder], %[remainder], #1\n"
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" vcvt.s32.f32 q0, q0, #31\n"
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" vqrshrn.s32 d0, q0, #16\n"
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" vst1.16 { d0[0] }, [%[d]], %[stride]\n"
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" bne 3b\n"
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"4:"
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: [d] "+r" (d), [s] "+r" (s), [n_samples] "+r" (n_samples),
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[remainder] "+r" (remainder)
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: [stride] "r" (stride)
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: "cc", "q0");
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#endif
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#endif
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}
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}
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