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impl-port: input ports read from io cycle & 1

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Input ports read from the async buffer cycle & 1 and output ports write
to (cycle + 1) & 1
This commit is contained in:
Wim Taymans 2024-05-08 10:40:14 +02:00
parent 9d94db6646
commit 03d62dc756
1 changed files with 1 additions and 1 deletions
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2
src/pipewire/impl-port.c
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@ -317,7 +317,7 @@ static int schedule_mix_input(void *object)
struct pw_impl_port *this = &impl->this; struct pw_impl_port *this = &impl->this;
struct spa_io_buffers *io = &this->rt.io; struct spa_io_buffers *io = &this->rt.io;
struct pw_impl_port_mix *mix; struct pw_impl_port_mix *mix;
uint32_t cycle = (this->node->rt.position->clock.cycle + 1) & 1; uint32_t cycle = this->node->rt.position->clock.cycle & 1;
if (SPA_UNLIKELY(PW_IMPL_PORT_IS_CONTROL(this))) if (SPA_UNLIKELY(PW_IMPL_PORT_IS_CONTROL(this)))
return SPA_STATUS_HAVE_DATA | SPA_STATUS_NEED_DATA; return SPA_STATUS_HAVE_DATA | SPA_STATUS_NEED_DATA;