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39 lines
No EOL
1.3 KiB
Text
39 lines
No EOL
1.3 KiB
Text
TRAM setup:
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TCBS (0x44) and TCB (0x41) has same meaning as on SB Live
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Internal TRAM size is 0x4000
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Max external TRAM size is 0x100000 - as on SB Live
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Register description:
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0xdb - Internal TRAM Delay Base Address Counter
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0xde - External TRAM Delay Base Address Counter
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0x100 - 0x1ff - tram access control registers (?)
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- only 5 bit valid
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bit : 4 - 0 - use log. compresion on write and read
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1 - use raw access - data from/to tram are read/wrote
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as 16 bit samples
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bits : 321 - ???
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001 - read from tram
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010 - read from tram
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011 - write to tram + 0111, 1001
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100 - read from tram
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101 - read from tram
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110 - read from tram
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others - ?????
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bit: 0 - 0 - normal mode
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1 - clear tram - set to data register valid address
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until TRAM counter reaches this address, reads from
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tram will return 0, then this flag is zeroed and
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tram is working in normal mode, working for read
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0x200 - 0x2ff - tram access data registers
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- same as on SB Live
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0x300 - 0x3ff - tram access address registers
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- address format - host: 32 bit offset 20 bit integer part + 12 bit fractional part
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to set offset to 0x123(SB Live) - 0x123 << 11 (Audigy)
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- address format - DSP: same as SB Live ???
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internal TRAM has index 0x00 - 0xbf
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external TRAM has index 0xc0 - 0xff |