Add ld10k1 tool

Added ld10k1 tool by Peter Zubaj.
This commit is contained in:
Takashi Iwai 2005-03-18 13:40:44 +00:00
parent 37104ebf62
commit 2df1aa7c20
98 changed files with 19970 additions and 1 deletions

View file

@ -0,0 +1 @@
EXTRA_DIST = README emu10k1MIDIEffects.tar.gz

2
ld10k1/contrib/README Normal file
View file

@ -0,0 +1,2 @@
These files are from holborn (Josep Andreu).
They are for SB Live.

View file

@ -0,0 +1,17 @@
name "3volBUS1"
include "emu_constants.asm"
;volBUS1 control #1,0,#1
inl IO
inr IO
in3 IO
out equ inl
acc3 out,inl,inr,in3
end

View file

@ -0,0 +1,18 @@
name "volBUS2"
include "emu_constants.asm"
;volBUS2 control #1,0,#1
inl IO
inr IO
in3 IO
out equ inl
acc3 out,inl,inr,in3
end

View file

@ -0,0 +1,34 @@
EXTRA_DIST = \
volBUS1.asm \
3volBUS2.asm \
emu_constants.asm \
freberv.asm \
gain_4.asm \
michorusL.asm \
michorusR.asm \
volLR.asm \
emu_constants.inc \
fv-basstreble.inc \
fv-controls.inc \
fv-filters-reduced.inc \
fv-filters.inc \
fv-routes.inc \
refl-big.inc \
refl-default.inc \
pontodo5
dist_effects_DATA = \
3volBUS1.emu10k1 \
3volBUS2.emu10k1 \
freberv.emu10k1 \
gain_4.emu10k1 \
michorusL.emu10k1 \
michorusR.emu10k1 \
volLR.emu10k1
CLEANFILES = $(dist_effects_DATA)
SUFFIXEC = .asm .emu10k1
.asm.emu10k1:
as10k1 -o $@ $<

View file

@ -0,0 +1,117 @@
;some hardware constants C_[n]<DecimalValue>, 'n' indicates negative value
;
;these are in 2's complement representation
C_0 equ $040 ;;00000000
C_1 equ $041 ;;00000001
C_2 equ $042 ;;00000002
C_3 equ $043 ;;00000003
C_4 equ $044 ;;00000004
C_8 equ $045 ;;00000008
C_16 equ $046 ;;00000010
C_32 equ $047 ;;00000020
C_256 equ $048 ;;00000100
C_65536 equ $049 ;;00010000
C_2^23 equ $04A ;;00080000
C_2^28 equ $04b ;;10000000
C_2^29 equ $04c ;;20000000 (C_max /4) +1
C_2^30 equ $04d ;;40000000 ( C_max / 2 ) + 1 (almost half)
C_nmax equ $04e ;;80000000 most negative number
C_max equ $04f ;;7fffffff most positive number
C_n1 equ $050 ;;ffffffff -1
C_n2 equ $051 ;;fffffffe -2
C_n2^30 equ $052 ;;c0000000 C_nmax /2
C_LSshift equ $55 ;;to left shift an address by using macsints
;;for fractional addresses
ZERO equ C_0;
ONE equ C_1;
;;; Hardware Registers:
ACCUM equ $56
CCR equ $57
NOISE1 equ $58
NOISE2 equ $59
IRQ equ $5A
DBAC equ $5B
and macro dest,srcA,srcB
andxor dest,srcA,srcB,C_0
endm
xor macro dest,srcA,srcB
andxor dest,C_n1,srcA,srcB
endm
not macro dest,src
andxor dest,src,C_n1,C_n1
endm
nand macro dest,srcA,srcB
andxor dest,srcA,srcB,C_n1
endm
or macro dest,srcA,srcB
not C_0,srcA
andxor dest,ACCUM,srcA,srcB
endm
nor macro dest,srcA,scrB
not dest,srcA
andxor dest,srcB,dest,srcA
not dest,dest
endm
neg macro dest,src
macs1 dest,C_0,C_1,C_nmax
endm
;;; branch on:
;;; ==0
beq macro count
skip CCR,CCR,C_8,count
endm
;;; !=0
bne macro count
skip CCR,CCR,C_256,count
endm
;;; <0
blt macro count
skip CCR,CCR,C_4,count
endm
;;; always branch
bra macro count
skip C_0,C_max,C_max,count
endm
;;; on saturation
bsa macro count
skip CCR,CCR,C_16,count
endm
bge macro count
C___80 con $80
skip CCR,CCR,C___80,count
endm
bgt macro count
C___180 con $180
skip CCR,CCR,C___180,count
endm
move macro dest,src
macs dest,src,C_0,C_0
endm
end
;;; usefull for testing values before a skip
test macro test
macs C_0,test,C_0,C_0
endm
cmp macro src1.scr2
macints C_0,src1,C_n1,src2
endm

View file

@ -0,0 +1,118 @@
;some hardware constants C_[n]<DecimalValue>, 'n' indicates negative value
;
;these are in 2's complement representation
C_0 equ $040 ;;00000000
C_1 equ $041 ;;00000001
C_2 equ $042 ;;00000002
C_3 equ $043 ;;00000003
C_4 equ $044 ;;00000004
C_8 equ $045 ;;00000008
C_16 equ $046 ;;00000010
C_32 equ $047 ;;00000020
C_256 equ $048 ;;00000100
C_65536 equ $049 ;;00010000
C_2^23 equ $04A ;;00080000
C_2^28 equ $04b ;;10000000
C_2^29 equ $04c ;;20000000 (C_max /4) +1
C_2^30 equ $04d ;;40000000 ( C_max / 2 ) + 1 (almost half)
C_nmax equ $04e ;;80000000 most negative number
C_max equ $04f ;;7fffffff most positive number
C_n1 equ $050 ;;ffffffff -1
C_n2 equ $051 ;;fffffffe -2
C_n2^30 equ $052 ;;c0000000 C_nmax /2
C_LSshift equ $55 ;;to left shift an address by using macsints
;;for fractional addresses
ZERO equ C_0;
ONE equ C_1;
;;; Hardware Registers:
ACCUM equ $56
CCR equ $57
NOISE1 equ $58
NOISE2 equ $59
IRQ equ $5A
DBAC equ $5B
and macro dest,srcA,srcB
andxor dest,srcA,srcB,C_0
endm
xor macro dest,srcA,srcB
andxor dest,C_n1,srcA,srcB
endm
not macro dest,src
andxor dest,src,C_n1,C_n1
endm
nand macro dest,srcA,srcB
andxor dest,srcA,srcB,C_n1
endm
or macro dest,srcA,srcB
not C_0,srcA
andxor dest,ACCUM,srcA,srcB
endm
nor macro dest,srcA,scrB
not dest,srcA
andxor dest,srcB,dest,srcA
not dest,dest
endm
neg macro dest,src
macs1 dest,C_0,C_1,C_nmax
endm
;;; branch on:
;;; ==0
beq macro count
skip CCR,CCR,C_8,count
endm
;;; !=0
bne macro count
skip CCR,CCR,C_256,count
endm
;;; <0
blt macro count
skip CCR,CCR,C_4,count
endm
;;; always branch
bra macro count
skip C_0,C_max,C_max,count
endm
;;; on saturation
bsa macro count
skip CCR,CCR,C_16,count
endm
bge macro count
C___80 con $80
skip CCR,CCR,C___80,count
endm
bgt macro count
C___180 con $180
skip CCR,CCR,C___180,count
endm
move macro dest,src
macs dest,src,C_0,C_0
endm
;;; usefull for testing values before a skip
test macro test
macs C_0,test,C_0,C_0
endm
cmp macro src1,scr2
macints C_0,src1,C_n1,src2
endm
end

View file

@ -0,0 +1,156 @@
;; fv10k1.m4 - fv10k1 package
;; This implements Jezar Wakefield's Freeverb algorithm
;;
;; Copyright (C) 2001 Oleg Smirnov <smirnov@astron.nl>
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
;;
;; $Id: fv10k1.m4,v 1.1 2001/09/28 01:56:20 dbertrand Exp $
name "Freeverb"
include "emu_constants.inc"
include "fv-routes.inc"
include "fv-controls.inc"
include "fv-basstreble.inc"
; IO lines right/left
ior io
iol io
; No room reflection support - load full set of Freeverb filters and put
; them into ITRAM first
include "fv-filters.inc"
; delay lines for channel & reverb predelay will use XTRAM
dlyr delay &2
dlyl delay &2
writer twrite dlyr,0
writel twrite dlyl,0
oreadr tread dlyr,64 ; use 64 samples to avoid some TRAM glitches
oreadl tread dlyl,64
revreadr tread dlyr,64
revreadl tread dlyl,64
input dyn 1 ; wet reverb input [== (inl+inr)*gain ]
dly_b2 sta 0,0 ; storage for second bass/treble filter
dly_t2 sta 0,0
dly_b3 sta 0,0
dly_t3 sta 0,0
dly_b4 sta 0,0
dly_t4 sta 0,0
reflr dyn 2
refll dyn 2
reverbr dyn 1
reverbl dyn 1
ptr dyn 2
ptl dyn 2
;;; update TRAM read addresses from control GPRs
acc3 oreadr.a,delay_r,writer.a,C_0
acc3 oreadl.a,delay_l,writel.a,C_0
acc3 revreadr.a,revdelay,writer.a,C_0
acc3 revreadl.a,revdelay,writel.a,C_0
;;; init reverb outputs (and clear ACCUM for code below)
macs fvrev_l,C_0,C_0,C_0
macs fvrev_r,C_0,C_0,C_0
;;; accumulate reverb inputs ( predelayed R+L * revgain )
;;; and at the same time pass input to output w/delay
macmv ior,oreadr,revreadr,revgain
macs input,ACCUM,revreadl,revgain
acc3 iol,oreadl,C_0,C_0
acc3 writer,ior,C_0,C_0
acc3 writel,iol,C_0,C_0
;;; apply & accumulate comb filters
do_comb_filters fvrev_l,fvrev_r
;;; apply allpass filters
do_allpass_filters fvrev_l,fvrev_r
;;; feed accumulated values to outputs, multiplying by wet & dry controls
interp tmp,fvrev_l,wet1,fvrev_r
interp tmpout,fvrev_r,wet1,fvrev_l
macs fvrev_l,tmp,revreadl,dry
macs fvrev_r,tmpout,revreadr,dry
;;; apply bass/treble controls to output
test revdefeat
bne .skipbasstreble
basstreble fvrev_l,fvrev_l,revbass,revtreble,dly_b1,dly_t1
basstreble fvrev_r,fvrev_r,revbass,revtreble,dly_b2,dly_t2
.skipbasstreble
;;; reset level meters at specified interval (use DBAC to track it)
andxor tmp,DBAC,level_interval,C_0
bne .skipreset
acc3 maxlev_fr,C_0,C_0,C_0
acc3 maxlev_fl,C_0,C_0,C_0
acc3 maxlev_rr,C_0,C_0,C_0
acc3 maxlev_rl,C_0,C_0,C_0
.skipreset
;;; apply reflection levels and bass/treble
macs reflr,C_0,fvrefl_fr,refl_f
macs refll,C_0,fvrefl_fl,refl_f
macs reflr,reflr,fvrefl_rr,refl_f ; two-speaker mode - add in other line
macs refll,refll,fvrefl_rl,refl_f
;;; apply reverb levels
macs reverbr,C_0,fvrev_r,reverb_f
macs reverbl,C_0,fvrev_l,reverb_f
;;; write in+reverb_reflections to output
;;; use macmv accumulation for extra precision
makeoutput MACRO io,refl,reverb,passthru
macs C_0,C_0,C_0,C_0
macmv tmp,tmp,refl,C_max
macmv tmp,C_0,io,ptf_level
macs io,ACCUM,reverb,C_max
ENDM
makeoutput ior,reflr,reverbr,ptr
makeoutput iol,refll,reverbl,ptl
;;; maintain the maximum level
maxlevel MACRO io,maxlev
tstneg tmp,io,io,C_0 ; tmp = abs(io)
limit maxlev,tmp,tmp,maxlev ; maxlevel=max(tmp,maxlevel)
ENDM
maxlevel ior.o,maxlev_fr
maxlevel iol.o,maxlev_fl
END

View file

@ -0,0 +1,112 @@
;; fv-basstreble.m4 - fv10k1 package
;; Defines macros for bass/treble filters
;;
;; This is wholly derived from Daniel Bertrand's tone.asm in the emu10k1
;; driver (see emu10k1/utils/as10k1/effects/tone.asm).
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
;;
;; $Id: fv-basstreble.inc,v 1.1 2001/09/28 01:56:20 dbertrand Exp $
;;; a and b coefs for bass:
b_b con 2.736129417e-01 5.240710533e-01 2.620355267e-01
a_b con 9.560258858e-01 -4.576868881e-01
;;; a and b coef for treble:
b_t con -4.982305773e-01 9.964611547e-01 -4.982305773e-01
a_t con 9.317583774e-01 -4.356836381e-01
scalein con 2.449e-05, 1.157407407e-04
scaleout con 128, 16192
dly_b1 sta 0,0
dly_t1 sta 0,0
tmp dyn 1 ; miscellaneous temp storage
tmpout dyn 1
;;; end of bass/treble definitions
;;;
;;; This macro applies the bass/treble controls (based on eq2.asm)
;;;
basstreble MACRO dest,source,tone_bass,tone_treble,dly_b,dly_t
;;; tone_bass filter(iir):
macw tmp, C_0, dly_b+1, a_b+1
macw tmp, tmp, dly_b , a_b
macw tmp,tmp,source,scalein
macints tmp, C_0, tmp, C_2
macs C_0,C_0,C_0,C_0
macmv dly_b+1,dly_b, dly_b+1, b_b+2
macmv dly_b,tmp, dly_b, b_b+1
macw tmp,ACCUM, tmp, b_b
macs tmp,C_0,tone_bass,tmp
macints tmpout,C_0,tmp,scaleout
;;; tone_treble
macw tmp, C_0, dly_t+1, a_t+1
macw tmp, tmp, dly_t , a_t
macw tmp, tmp, source,scalein+1
macints tmp,C_0,tmp,C_2
macs C_0,C_0,C_0,C_0
macmv dly_t+1,dly_t, dly_t+1, b_t+2
macmv dly_t,tmp, dly_t, b_t+1
macw tmp,ACCUM, tmp, b_t
macs tmp,C_0,tone_treble,tmp
macints dest,tmpout,tmp,scaleout+1
ENDM
;;;
;;; This macro applies the bass/treble controls (based on eq2.asm)
;;; and stores results into two separate GPRs
;;;
basstreblesep MACRO dest_b,dest_t,source,tone_bass,tone_treble,dly_b,dly_t
;;; tone_bass filter(iir):
macw tmp, C_0, dly_b+1, a_b+1
macw tmp, tmp, dly_b , a_b
macw tmp,tmp,source,scalein
macints tmp, C_0, tmp, C_2
macs C_0,C_0,C_0,C_0
macmv dly_b+1,dly_b, dly_b+1, b_b+2
macmv dly_b,tmp, dly_b, b_b+1
macw tmp,ACCUM, tmp, b_b
macs tmp,C_0,tone_bass,tmp
macints tmpout,C_0,tmp,scaleout
;;; tone_treble
macw tmp, C_0, dly_t+1, a_t+1
macw tmp, tmp, dly_t , a_t
macw tmp, tmp, source,scalein+1
macints tmp,C_0,tmp,C_2
macs C_0,C_0,C_0,C_0
macmv dly_t+1,dly_t, dly_t+1, b_t+2
macmv dly_t,tmp, dly_t, b_t+1
macw tmp,ACCUM, tmp, b_t
macs tmp,C_0,tone_treble,tmp
macints dest_t,C_0,tmp,scaleout+1
acc3 dest_b,tmpout,C_0,C_0
ENDM
END

View file

@ -0,0 +1,121 @@
;; fv-controls.asm - fv10k1 package
;; Defines control GPRs for the fv10k1 package
;;
;; Copyright (C) 2001 Oleg Smirnov <smirnov@astron.nl>
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
;;
;; $Id: fv-controls.inc,v 1.1 2001/09/28 01:56:20 dbertrand Exp $
; debugging registers
;debug control #0,#0,#1
;debug2 control #0,#0,#1
;debug3 control #0,#0,#1
;debug4 control #0,#0,#1
; This delay is applied to the input before passing it through
; to the output. Note that this is independent of the room reflections
; or reverb delays, and mainly intended to compensate for pathlength
; differential in an environment where the speakers are not equidistant
; from the listening position (i.e. a car!). 1/Vsound is about 3 ms/m.
delay_r control &0,&0,&0.8
delay_l control &0,&0,&0.8
; high-frequency damping for room reflections
refldamp control #0,#0,#1
; delay for start of reverbrations. Note that this control is ignored
; when using input patches with a room reflection engine -- there we use
; a constant revdelay instead.
revdelay control &.002,&0,&1
; gains for "wet" reverbrations
revgain control #0.10,#0,#1
; room size parameter, 0-1. Bigger values produce deeper reverb.
roomsize control #.90,#0,#1
; room dampening 0-1
damp control #.2,#0,#1
; allpass filter feedback -- normally constant at .5
allpassfeed control #.2,#0,#1
; "wet1" level controls the amount of left/right reverb intermixing:
; L = L*(1-wet1) + R*wet1
; R = R*(1-wet1) + L*wet1
; (original Freeverb uses wet1 and wet2, computed from "wet" and "width":
; wet1 = wet*(width+1)/2
; wet2 = wet*(1-width)/2 )
wet1 control #0,#0,#1
; "dry" reverb level:
; output = reverb + input*dry
; Note that this is somewhat different from the "passthru" level, since
; reverb bass/treble [and predelay, if any] are applied to the dry signal,
; but not to the passthru signal
dry control #0,#0,#1
; bass and treble controls for the reverb engine
revbass control #0,#0,#1
revtreble control #0,#0,#1
; set to 1 to skip reverb bass/treble filters
revdefeat control #1,#0,#1
; fractional levels of reflections for F and R speakers
refl_f control #0,#0,#1
refl_r control #0,#0,#1
; additional integer gains for rear reflections
refl_rgain control #0,#0,#1
; fractional levels of reverbs for F and R speakers
reverb_f control #0.8,#0,#1
reverb_r control #0.0,#0,#1
; additional integer gains for rear reverbs
reverb_rgain control #0,#0,#1
; passthru controls (separate for front/rear)
; output = input*passthru + reverbs + reflections
ptf_level control #1,#0,#1
ptr_level control #0,#0,#1
; additional integer gains for rear passthru
ptr_gain control #0,#0,#1
; separate bass/treble controls are available for the rear passthrus
ptr_bass control #0,#0,#1
ptr_treble control #0,#0,#1
ptr_defeat control #0,#0,1
; Max output level meters. Output patches update these GPRs with the
; maximum output level encountered.
maxlev_fr control #1,#0,#1
maxlev_fl control #1,#0,#1
maxlev_rr control #.0,#0,#1
maxlev_rl control #.0,#0,#1
; interval at which level meters are reset. For an interval of 2N samples,
; it should be set to (2^N-1)*$800.
; The DBAC register is ANDed by this value, and if the result is 0,
; the meters are reset. $800 corresponds to 1 sample.
; $0efff00 is 4096 samples
; $0fffE00 is 8192 samples
; $1fffC00 is 16384 samples
; $3fff800 is 32768 samples
; $7fff800 is 65536 samples
level_interval control $1fffC00,$0,$8000000
END

View file

@ -0,0 +1,174 @@
;; fv-filters.m4 - fv10k1 package
;; defines delay lines and GPRs for Freeverb's comb and allpass filters
;;
;; Copyright (C) 2001 Oleg Smirnov <smirnov@astron.nl>
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
;;
;; $Id: fv-filters.m4,v 1.1 2001/09/28 01:56:20 dbertrand Exp $
; This is a shorter version that only uses 32 address lines
;;; macro to apply & accumulate a comb filter
comb MACRO dest,rdelay,wdelay,filterstore
acc3 dest,dest,rdelay,C_0
interp filterstore,rdelay,damp,filterstore
macs wdelay,input,filterstore,roomsize
endm
;;; macro to apply an allpass filter
allpass MACRO dest,rdelay,wdelay
macs wdelay,dest,rdelay,allpassfeed
macs1 dest,rdelay,dest,C_max
endm
;;; Freeverb reduced mode - comb filter delay lines go ahead, since for
;;; reduced Freeverb we do not want to use internal TRAM -- it may be out
;;; of address lines thanks to the reflection engine, so external TRAM
;;; is preferrable. Hence longer delays (for comb filters) go first.
;;; Freeverb reduced mode - 4 comb filters only
csl5 sta 0
csr5 sta 0
cdl5 delay 1569
cdr5 delay 1594
wcdl5 twrite cdl5,0
wcdr5 twrite cdr5,0
rcdl5 tread cdl5,1549
rcdr5 tread cdr5,1574
csl6 sta 0
csr6 sta 0
cdl6 delay 1645
cdr6 delay 1670
wcdl6 twrite cdl6,0
wcdr6 twrite cdr6,0
rcdl6 tread cdl6,1625
rcdr6 tread cdr6,1650
csl7 sta 0
csr7 sta 0
cdl7 delay 1717
cdr7 delay 1742
wcdl7 twrite cdl7,0
wcdr7 twrite cdr7,0
rcdl7 tread cdl7,1697
rcdr7 tread cdr7,1722
csl8 sta 0
csr8 sta 0
cdl8 delay 1782
cdr8 delay 1807
wcdl8 twrite cdl8,0
wcdr8 twrite cdr8,0
rcdl8 tread cdl8,1762
rcdr8 tread cdr8,1787
;;; define macro to apply all comb filters to land r
do_comb_filters MACRO l,r
comb l,rcdl5,wcdl5,csl5
comb l,rcdl6,wcdl6,csl6
comb l,rcdl7,wcdl7,csl7
comb l,rcdl8,wcdl8,csl8
comb r,rcdr5,wcdr5,csr5
comb r,rcdr6,wcdr6,csr6
comb r,rcdr7,wcdr7,csr7
comb r,rcdr8,wcdr8,csr8
ENDM
;;; Now define the allpass filter delay lines
;;; 4 allpass filters
apl1 delay 626
apr1 delay 651
wapl1 twrite apl1,0
wapr1 twrite apr1,0
rapl1 tread apl1,606
rapr1 tread apr1,631
apl2 delay 500
apr2 delay 525
wapl2 twrite apl2,0
wapr2 twrite apr2,0
rapl2 tread apl2,480
rapr2 tread apr2,505
apl3 delay 391
apr3 delay 416
wapl3 twrite apl3,0
wapr3 twrite apr3,0
rapl3 tread apl3,371
rapr3 tread apr3,396
apl4 delay 265
apr4 delay 290
wapl4 twrite apl4,0
wapr4 twrite apr4,0
rapl4 tread apl4,245
rapr4 tread apr4,270
do_allpass_filters MACRO l,r
allpass l,rapl1,wapl1
allpass l,rapl2,wapl2
allpass l,rapl3,wapl3
allpass l,rapl4,wapl4
allpass r,rapr1,wapr1
allpass r,rapr2,wapr2
allpass r,rapr3,wapr3
allpass r,rapr4,wapr4
ENDM
END

View file

@ -0,0 +1,227 @@
;; fv-filters.m4 - fv10k1 package
;; defines delay lines and GPRs for Freeverb's comb and allpass filters
;;
;; Copyright (C) 2001 Oleg Smirnov <smirnov@astron.nl>
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
;;
;; $Id: fv-filters.m4,v 1.1 2001/09/28 01:56:20 dbertrand Exp $
;;; macro to apply & accumulate a comb filter
comb MACRO dest,rdelay,wdelay,filterstore
acc3 dest,dest,rdelay,C_0
interp filterstore,rdelay,damp,filterstore
macs wdelay,input,filterstore,roomsize
endm
;;; macro to apply an allpass filter
allpass MACRO dest,rdelay,wdelay
macs wdelay,dest,rdelay,allpassfeed
macs1 dest,rdelay,dest,C_max
endm
;
;;; Freeverb full mode - allpass filter delay lines go ahead, since
;;; wed rather use internal TRAM. Hence shorter delays go first.
;;; 4 allpass filters
apl1 delay 626
apr1 delay 651
wapl1 twrite apl1,0
wapr1 twrite apr1,0
rapl1 tread apl1,606
rapr1 tread apr1,631
apl2 delay 500
apr2 delay 525
wapl2 twrite apl2,0
wapr2 twrite apr2,0
rapl2 tread apl2,480
rapr2 tread apr2,505
apl3 delay 391
apr3 delay 416
wapl3 twrite apl3,0
wapr3 twrite apr3,0
rapl3 tread apl3,371
rapr3 tread apr3,396
apl4 delay 265
apr4 delay 290
wapl4 twrite apl4,0
wapr4 twrite apr4,0
rapl4 tread apl4,245
rapr4 tread apr4,270
do_allpass_filters MACRO l,r
allpass l,rapl1,wapl1
allpass l,rapl2,wapl2
allpass l,rapl3,wapl3
allpass l,rapl4,wapl4
allpass r,rapr1,wapr1
allpass r,rapr2,wapr2
allpass r,rapr3,wapr3
allpass r,rapr4,wapr4
ENDM
;;; Now define the comb filter delay lines
;;; Freeverb full mode - 8 comb filters
csl1 sta 0
csr1 sta 0
cdl1 delay 1236
cdr1 delay 1261
wcdl1 twrite cdl1,0
wcdr1 twrite cdr1,0
rcdl1 tread cdl1,1216
rcdr1 tread cdr1,1241
csl2 sta 0
csr2 sta 0
cdl2 delay 1314
cdr2 delay 1339
wcdl2 twrite cdl2,0
wcdr2 twrite cdr2,0
rcdl2 tread cdl2,1294
rcdr2 tread cdr2,1319
csl3 sta 0
csr3 sta 0
cdl3 delay 1411
cdr3 delay 1436
wcdl3 twrite cdl3,0
wcdr3 twrite cdr3,0
rcdl3 tread cdl3,1391
rcdr3 tread cdr3,1416
csl4 sta 0
csr4 sta 0
cdl4 delay 1498
cdr4 delay 1523
wcdl4 twrite cdl4,0
wcdr4 twrite cdr4,0
rcdl4 tread cdl4,1478
rcdr4 tread cdr4,1503
csl5 sta 0
csr5 sta 0
cdl5 delay 1569
cdr5 delay 1594
wcdl5 twrite cdl5,0
wcdr5 twrite cdr5,0
rcdl5 tread cdl5,1549
rcdr5 tread cdr5,1574
csl6 sta 0
csr6 sta 0
cdl6 delay 1645
cdr6 delay 1670
wcdl6 twrite cdl6,0
wcdr6 twrite cdr6,0
rcdl6 tread cdl6,1625
rcdr6 tread cdr6,1650
csl7 sta 0
csr7 sta 0
cdl7 delay 1717
cdr7 delay 1742
wcdl7 twrite cdl7,0
wcdr7 twrite cdr7,0
rcdl7 tread cdl7,1697
rcdr7 tread cdr7,1722
csl8 sta 0
csr8 sta 0
cdl8 delay 1782
cdr8 delay 1807
wcdl8 twrite cdl8,0
wcdr8 twrite cdr8,0
rcdl8 tread cdl8,1762
rcdr8 tread cdr8,1787
do_comb_filters MACRO l,r
comb l,rcdl1,wcdl1,csl1
comb l,rcdl2,wcdl2,csl2
comb l,rcdl3,wcdl3,csl3
comb l,rcdl4,wcdl4,csl4
comb l,rcdl5,wcdl5,csl5
comb l,rcdl6,wcdl6,csl6
comb l,rcdl7,wcdl7,csl7
comb l,rcdl8,wcdl8,csl8
comb r,rcdr1,wcdr1,csr1
comb r,rcdr2,wcdr2,csr2
comb r,rcdr3,wcdr3,csr3
comb r,rcdr4,wcdr4,csr4
comb r,rcdr5,wcdr5,csr5
comb r,rcdr6,wcdr6,csr6
comb r,rcdr7,wcdr7,csr7
comb r,rcdr8,wcdr8,csr8
ENDM
;'
END

View file

@ -0,0 +1,37 @@
;; fv-routes.asm - fv10k1 package
;; Defines routing GPRs
;;
;; Copyright (C) 2001 Oleg Smirnov <smirnov@astron.nl>
;;
;; This program is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2 of the License, or
;; (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
;;
;; $Id: fv-routes.inc,v 1.1 2001/09/28 01:56:20 dbertrand Exp $
; These registers are used to pass samples from the fv10k1 engine.
; fv10k1 attaches to two (R+L) input lines, and generates three sets
; of outputs: reverbs, reflections front, reflections rear.
; Separate output patches are responsible for mixing these outputs
; into their respective output lines
fvrev_r control #1,#0,#1
fvrev_l control #1,#0,#1
; Directional outputs of room reflection engine
fvrefl_fl control #1,#0,#1
fvrefl_rl control #0,#0,#1
fvrefl_fr control #1,#0,#1
fvrefl_rr control #0,#0,#1
END

View file

@ -0,0 +1,19 @@
name "4-channel Gain"
;;; The next line controls the amount of gain (must be an integer)
gain constant 4
signal1 io
signal2 io
signal3 io
signal4 io
macints signal1, $40, signal1, gain ; signal= 0 + signal * gain
macints signal2, $40, signal2, gain
macints signal3, $40, signal3, gain
macints signal4, $40, signal4, gain
end

View file

@ -0,0 +1,87 @@
;;; Simple Chorus
;;; Author:Daniel Bertrand
;;; Date: Oct 12, 2000
;;; This program is free software; you can redistribute it and/or modify
;;; it under the terms of the GNU General Public License as published by
;;; the Free Software Foundation; either version 2 of the License, or
;;; (at your option) any later version.
;;; References:
;;; http://www.harmony-central.com/Effects/Articles/Chorus
;;; speed(formerly "delta")=2*pi*freq/48000
;;; this give us our delta value for a specific freq (0.1-0.3Hz is good)
include "emu_constants.asm"
name "ChorusL"
in IO
outl equ in
speedL control 4e-05 , 0 , 1e-4 ; Controls frequency (radians)
delayL control &32e-3 ,&10e-3 , &80e-3; twice (2*) average delay (sec)
widthL control #0.8 ,0 ,#1 ; width control
mixL control #1 ,0 ,#1 ; forward mix
;; sine generator storage spaces:
sinx sta 0
cosx sta #0.5
tmp dyn
tmp2 dyn
;;; Two Delay Lines:
dly delay &80e-3 ;10msec delay line
write twrite dly,0 ; tram writes
ready tread dly,0 ; tram reads
reada tread dly,0
;;;The code:
;;; two opcode sinewave generator (I love this chip!):
macs sinx,sinx,speedL,cosx
macs1 cosx,cosx,speedL,sinx
;;; 0.5Asint+0.5:
macs tmp,C_2^30,sinx,widthL
;;; calculate address:
macs ready.a,write.a,delayL,tmp
;second addresses for interpolation:
;(interesting how the emu engineers decided that $800 wasn't a needed value)
macints reada.a,ready.a,C_8,C_256
;;; Write to the delay line:
macs write,C_0,in,C_2^29
;;; output values:
;;; 0x55 is 00100000 (?)
macints tmp,C_0,reada.a,C_LSshift; get least significant part of address
interp tmp2,ready,tmp,reada ;interpolate in-between the two delay line readings
macs outl,tmp2,tmp2,mixL
end

View file

@ -0,0 +1,87 @@
;;; Simple Chorus
;;; Author:Daniel Bertrand
;;; Date: Oct 12, 2000
;;; This program is free software; you can redistribute it and/or modify
;;; it under the terms of the GNU General Public License as published by
;;; the Free Software Foundation; either version 2 of the License, or
;;; (at your option) any later version.
;;; References:
;;; http://www.harmony-central.com/Effects/Articles/Chorus
;;; speed(formerly "delta")=2*pi*freq/48000
;;; this give us our delta value for a specific freq (0.1-0.3Hz is good)
include "emu_constants.asm"
name "ChorusR"
in IO
outr equ in
speedR control 5e-05 , 0 , 1e-4 ; Controls frequency (radians)
delayR control &30e-3 ,&10e-3 , &80e-3; twice (2*) average delay (sec)
widthR control #0.78 ,0 ,#1 ; width control
mixR control #1 ,0 ,#1 ; forward mix
;; sine generator storage spaces:
sinx sta 0
cosx sta #0.5
tmp dyn
tmp2 dyn
;;; Two Delay Lines:
dly delay &80e-3 ;10msec delay line
write twrite dly,0 ; tram writes
ready tread dly,0 ; tram reads
reada tread dly,0
;;;The code:
;;; two opcode sinewave generator (I love this chip!):
macs sinx,sinx,speedR,cosx
macs1 cosx,cosx,speedR,sinx
;;; 0.5Asint+0.5:
macs tmp,C_2^30,sinx,widthR
;;; calculate address:
macs ready.a,write.a,delayR,tmp
;second addresses for interpolation:
;(interesting how the emu engineers decided that $800 wasn't a needed value)
macints reada.a,ready.a,C_8,C_256
;;; Write to the delay line:
macs write,C_0,in,C_2^29
;;; output values:
;;; 0x55 is 00100000 (?)
macints tmp,C_0,reada.a,C_LSshift; get least significant part of address
interp tmp2,ready,tmp,reada ;interpolate in-between the two delay line readings
macs outr,tmp2,tmp2,mixR
end

View file

@ -0,0 +1,64 @@
#Reset DSP
lo10k1 -s
#load MASTER L,R
lo10k1 -n -a volLR.emu10k1
#load Bus L and BUS R
lo10k1 -n -a 3volBUS1.emu10k1
lo10k1 -n -a 3volBUS2.emu10k1
#load Chorus Effect
lo10k1 -n -a michorusL.emu10k1
lo10k1 -n -a michorusR.emu10k1
#load gain
lo10k1 -n -a gain_4.emu10k1
#load reverb
lo10k1 -n -a freberv.emu10k1
lo10k1 -q "PIN(5,0)=FX(4)"
lo10k1 -q "PIN(5,1)=FX(5)"
lo10k1 -q "PIN(5,2)=FX(13)"
lo10k1 -q "PIN(5,3)=FX(13)"
#Input Chorus with FX(13) MIDI_Chorus_FX
lo10k1 -q "PIN(3)=POUT(5,2)"
lo10k1 -q "PIN(4)=POUT(5,3)"
#reverb
lo10k1 -q "PIN(6,0)=FX(12)"
lo10k1 -q "PIN(6,1)=FX(12)"
#Mix in BUS L FX_MIDI_Left + Chorus Effect
lo10k1 -q "PIN(1,1)=POUT(5,0)"
lo10k1 -q "PIN(1,0)=POUT(3)"
lo10k1 -q "PIN(1,2)=POUT(6,0)"
#Mix in BUS R FX:MIDI_Right + Chorus Effect
lo10k1 -q "PIN(2,1)=POUT(5,1)"
lo10k1 -q "PIN(2,0)=POUT(4)"
lo10k1 -q "PIN(2,2)=POUT(6,1)"
#BUS L to Master L
lo10k1 -q "PIN(0,0)=POUT(1,0)"
#BUS R to Master R
lo10k1 -q "PIN(0,1)=POUT(2,0)"
#Master to Ouputs
lo10k1 -q "POUT(0,0)=OUT(0)"
lo10k1 -q "POUT(0,1)=OUT(1)"

View file

@ -0,0 +1,337 @@
;;; FV10K1 room relections code
;;; Generates room reflections according to file big.room.rp, and stores
;;; them in GPRs fvrefl_[fl|fr|rl|rr].
;;; Built on Sat Jan 24 13:18:00 2004 from room definition file big.room.rp.
; define delays and dampening constants
readr0 tread dlyr,&0.070249
readl0 tread dlyl,&0.070249
fl0 constant #-0.028783
fr0 constant #-0.011243
dmpstore_r0 sta 0,0,0
dmpstore_l0 sta 0,0,0
readr1 tread dlyr,&0.070249
readl1 tread dlyl,&0.070249
fl1 constant #-0.011243
fr1 constant #-0.028783
dmpstore_r1 sta 0,0,0
dmpstore_l1 sta 0,0,0
readr2 tread dlyr,&0.059064
readl2 tread dlyl,&0.059064
fl2 constant #0.054798
fr2 constant #0.021405
dmpstore_r2 sta 0,0
dmpstore_l2 sta 0,0
readr3 tread dlyr,&0.059064
readl3 tread dlyl,&0.059064
fl3 constant #0.021405
fr3 constant #0.054798
dmpstore_r3 sta 0,0
dmpstore_l3 sta 0,0
readr4 tread dlyr,&0.001778
readl4 tread dlyl,&0.001778
fl4 constant #-0.428866
fr4 constant #-0.167526
dmpstore_r4 sta 0
dmpstore_l4 sta 0
readr5 tread dlyr,&0.001778
readl5 tread dlyl,&0.001778
fl5 constant #-0.167526
fr5 constant #-0.428866
dmpstore_r5 sta 0
dmpstore_l5 sta 0
readr6 tread dlyr,&0.048126
readl6 tread dlyl,&0.048126
fl6 constant #-0.106417
fr6 constant #-0.041569
dmpstore_r6 sta 0
dmpstore_l6 sta 0
readr7 tread dlyr,&0.048126
readl7 tread dlyl,&0.048126
fl7 constant #-0.041569
fr7 constant #-0.106417
dmpstore_r7 sta 0
dmpstore_l7 sta 0
readr8 tread dlyr,&0.059064
readl8 tread dlyl,&0.059064
fl8 constant #0.054798
fr8 constant #0.021405
dmpstore_r8 sta 0,0
dmpstore_l8 sta 0,0
readr9 tread dlyr,&0.059064
readl9 tread dlyl,&0.059064
fl9 constant #0.021405
fr9 constant #0.054798
dmpstore_r9 sta 0,0
dmpstore_l9 sta 0,0
readr10 tread dlyr,&0.077324
readl10 tread dlyl,&0.077324
fr10 constant #-0.047167
rr10 constant #-0.002611
dmpstore_r10 sta 0,0,0
dmpstore_l10 sta 0,0,0
readr11 tread dlyr,&0.051184
readl11 tread dlyl,&0.051184
fr11 constant #0.103186
rr11 constant #0.012640
dmpstore_r11 sta 0,0
dmpstore_l11 sta 0,0
readr12 tread dlyr,&0.035389
readl12 tread dlyl,&0.035389
fr12 constant #0.160243
rr12 constant #0.008872
dmpstore_r12 sta 0,0
dmpstore_l12 sta 0,0
readr13 tread dlyr,&0.050379
readl13 tread dlyl,&0.050379
fr13 constant #-0.161577
rr13 constant #-0.019793
dmpstore_r13 sta 0
dmpstore_l13 sta 0
readr14 tread dlyr,&0.034414
readl14 tread dlyl,&0.034414
fr14 constant #-0.252993
rr14 constant #-0.014007
dmpstore_r14 sta 0
dmpstore_l14 sta 0
readr15 tread dlyr,&0.079794
readl15 tread dlyl,&0.079794
fr15 constant #0.065450
rr15 constant #0.008018
dmpstore_r15 sta 0,0
dmpstore_l15 sta 0,0
readr16 tread dlyr,&0.068240
readl16 tread dlyl,&0.068240
fr16 constant #0.085203
rr16 constant #0.004717
dmpstore_r16 sta 0,0
dmpstore_l16 sta 0,0
readr17 tread dlyr,&0.077324
readl17 tread dlyl,&0.077324
fr17 constant #-0.047167
rr17 constant #-0.002611
dmpstore_r17 sta 0,0,0
dmpstore_l17 sta 0,0,0
;;; Accumulate reflections for FL
interp dmpstore_l0+0,readl0,refldamp,dmpstore_l0+0
interp dmpstore_l0+1,dmpstore_l0+0,refldamp,dmpstore_l0+1
interp dmpstore_l0+2,dmpstore_l0+1,refldamp,dmpstore_l0+2
interp dmpstore_r0+0,readr0,refldamp,dmpstore_r0+0
interp dmpstore_r0+1,dmpstore_r0+0,refldamp,dmpstore_r0+1
interp dmpstore_r0+2,dmpstore_r0+1,refldamp,dmpstore_r0+2
interp dmpstore_r1+0,readr1,refldamp,dmpstore_r1+0
interp dmpstore_r1+1,dmpstore_r1+0,refldamp,dmpstore_r1+1
interp dmpstore_r1+2,dmpstore_r1+1,refldamp,dmpstore_r1+2
interp dmpstore_l1+0,readl1,refldamp,dmpstore_l1+0
interp dmpstore_l1+1,dmpstore_l1+0,refldamp,dmpstore_l1+1
interp dmpstore_l1+2,dmpstore_l1+1,refldamp,dmpstore_l1+2
interp dmpstore_l2+0,readl2,refldamp,dmpstore_l2+0
interp dmpstore_l2+1,dmpstore_l2+0,refldamp,dmpstore_l2+1
interp dmpstore_r2+0,readr2,refldamp,dmpstore_r2+0
interp dmpstore_r2+1,dmpstore_r2+0,refldamp,dmpstore_r2+1
interp dmpstore_r3+0,readr3,refldamp,dmpstore_r3+0
interp dmpstore_r3+1,dmpstore_r3+0,refldamp,dmpstore_r3+1
interp dmpstore_l3+0,readl3,refldamp,dmpstore_l3+0
interp dmpstore_l3+1,dmpstore_l3+0,refldamp,dmpstore_l3+1
interp dmpstore_l4+0,readl4,refldamp,dmpstore_l4+0
interp dmpstore_r4+0,readr4,refldamp,dmpstore_r4+0
interp dmpstore_r5+0,readr5,refldamp,dmpstore_r5+0
interp dmpstore_l5+0,readl5,refldamp,dmpstore_l5+0
interp dmpstore_l6+0,readl6,refldamp,dmpstore_l6+0
interp dmpstore_r6+0,readr6,refldamp,dmpstore_r6+0
interp dmpstore_r7+0,readr7,refldamp,dmpstore_r7+0
interp dmpstore_l7+0,readl7,refldamp,dmpstore_l7+0
interp dmpstore_l8+0,readl8,refldamp,dmpstore_l8+0
interp dmpstore_l8+1,dmpstore_l8+0,refldamp,dmpstore_l8+1
interp dmpstore_r8+0,readr8,refldamp,dmpstore_r8+0
interp dmpstore_r8+1,dmpstore_r8+0,refldamp,dmpstore_r8+1
interp dmpstore_r9+0,readr9,refldamp,dmpstore_r9+0
interp dmpstore_r9+1,dmpstore_r9+0,refldamp,dmpstore_r9+1
interp dmpstore_l9+0,readl9,refldamp,dmpstore_l9+0
interp dmpstore_l9+1,dmpstore_l9+0,refldamp,dmpstore_l9+1
interp dmpstore_l10+0,readl10,refldamp,dmpstore_l10+0
interp dmpstore_l10+1,dmpstore_l10+0,refldamp,dmpstore_l10+1
interp dmpstore_l10+2,dmpstore_l10+1,refldamp,dmpstore_l10+2
interp dmpstore_r11+0,readr11,refldamp,dmpstore_r11+0
interp dmpstore_r11+1,dmpstore_r11+0,refldamp,dmpstore_r11+1
interp dmpstore_l12+0,readl12,refldamp,dmpstore_l12+0
interp dmpstore_l12+1,dmpstore_l12+0,refldamp,dmpstore_l12+1
interp dmpstore_r13+0,readr13,refldamp,dmpstore_r13+0
interp dmpstore_l14+0,readl14,refldamp,dmpstore_l14+0
interp dmpstore_r15+0,readr15,refldamp,dmpstore_r15+0
interp dmpstore_r15+1,dmpstore_r15+0,refldamp,dmpstore_r15+1
interp dmpstore_l16+0,readl16,refldamp,dmpstore_l16+0
interp dmpstore_l16+1,dmpstore_l16+0,refldamp,dmpstore_l16+1
interp dmpstore_l17+0,readl17,refldamp,dmpstore_l17+0
interp dmpstore_l17+1,dmpstore_l17+0,refldamp,dmpstore_l17+1
interp dmpstore_l17+2,dmpstore_l17+1,refldamp,dmpstore_l17+2
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_l0+2,fl0
macmv tmp,C_0,dmpstore_r0+2,fr0
macmv tmp,C_0,dmpstore_r1+2,fl1
macmv tmp,C_0,dmpstore_l1+2,fr1
macmv tmp,C_0,dmpstore_l2+1,fl2
macmv tmp,C_0,dmpstore_r2+1,fr2
macmv tmp,C_0,dmpstore_r3+1,fl3
macmv tmp,C_0,dmpstore_l3+1,fr3
macmv tmp,C_0,dmpstore_l4+0,fl4
macmv tmp,C_0,dmpstore_r4+0,fr4
macmv tmp,C_0,dmpstore_r5+0,fl5
macmv tmp,C_0,dmpstore_l5+0,fr5
macmv tmp,C_0,dmpstore_l6+0,fl6
macmv tmp,C_0,dmpstore_r6+0,fr6
macmv tmp,C_0,dmpstore_r7+0,fl7
macmv tmp,C_0,dmpstore_l7+0,fr7
macmv tmp,C_0,dmpstore_l8+1,fl8
macmv tmp,C_0,dmpstore_r8+1,fr8
macmv tmp,C_0,dmpstore_r9+1,fl9
macmv tmp,C_0,dmpstore_l9+1,fr9
macmv tmp,C_0,dmpstore_l10+2,fr10
macmv tmp,C_0,dmpstore_r11+1,fr11
macmv tmp,C_0,dmpstore_l12+1,fr12
macmv tmp,C_0,dmpstore_r13+0,fr13
macmv tmp,C_0,dmpstore_l14+0,fr14
macmv tmp,C_0,dmpstore_r15+1,fr15
macmv tmp,C_0,dmpstore_l16+1,fr16
macs fvrefl_fl,ACCUM,dmpstore_l17+2,fr17
;;; Accumulate reflections for FR
interp dmpstore_l0+0,readl0,refldamp,dmpstore_l0+0
interp dmpstore_l0+1,dmpstore_l0+0,refldamp,dmpstore_l0+1
interp dmpstore_l0+2,dmpstore_l0+1,refldamp,dmpstore_l0+2
interp dmpstore_r0+0,readr0,refldamp,dmpstore_r0+0
interp dmpstore_r0+1,dmpstore_r0+0,refldamp,dmpstore_r0+1
interp dmpstore_r0+2,dmpstore_r0+1,refldamp,dmpstore_r0+2
interp dmpstore_r1+0,readr1,refldamp,dmpstore_r1+0
interp dmpstore_r1+1,dmpstore_r1+0,refldamp,dmpstore_r1+1
interp dmpstore_r1+2,dmpstore_r1+1,refldamp,dmpstore_r1+2
interp dmpstore_l1+0,readl1,refldamp,dmpstore_l1+0
interp dmpstore_l1+1,dmpstore_l1+0,refldamp,dmpstore_l1+1
interp dmpstore_l1+2,dmpstore_l1+1,refldamp,dmpstore_l1+2
interp dmpstore_l2+0,readl2,refldamp,dmpstore_l2+0
interp dmpstore_l2+1,dmpstore_l2+0,refldamp,dmpstore_l2+1
interp dmpstore_r2+0,readr2,refldamp,dmpstore_r2+0
interp dmpstore_r2+1,dmpstore_r2+0,refldamp,dmpstore_r2+1
interp dmpstore_r3+0,readr3,refldamp,dmpstore_r3+0
interp dmpstore_r3+1,dmpstore_r3+0,refldamp,dmpstore_r3+1
interp dmpstore_l3+0,readl3,refldamp,dmpstore_l3+0
interp dmpstore_l3+1,dmpstore_l3+0,refldamp,dmpstore_l3+1
interp dmpstore_l4+0,readl4,refldamp,dmpstore_l4+0
interp dmpstore_r4+0,readr4,refldamp,dmpstore_r4+0
interp dmpstore_r5+0,readr5,refldamp,dmpstore_r5+0
interp dmpstore_l5+0,readl5,refldamp,dmpstore_l5+0
interp dmpstore_l6+0,readl6,refldamp,dmpstore_l6+0
interp dmpstore_r6+0,readr6,refldamp,dmpstore_r6+0
interp dmpstore_r7+0,readr7,refldamp,dmpstore_r7+0
interp dmpstore_l7+0,readl7,refldamp,dmpstore_l7+0
interp dmpstore_l8+0,readl8,refldamp,dmpstore_l8+0
interp dmpstore_l8+1,dmpstore_l8+0,refldamp,dmpstore_l8+1
interp dmpstore_r8+0,readr8,refldamp,dmpstore_r8+0
interp dmpstore_r8+1,dmpstore_r8+0,refldamp,dmpstore_r8+1
interp dmpstore_r9+0,readr9,refldamp,dmpstore_r9+0
interp dmpstore_r9+1,dmpstore_r9+0,refldamp,dmpstore_r9+1
interp dmpstore_l9+0,readl9,refldamp,dmpstore_l9+0
interp dmpstore_l9+1,dmpstore_l9+0,refldamp,dmpstore_l9+1
interp dmpstore_r10+0,readr10,refldamp,dmpstore_r10+0
interp dmpstore_r10+1,dmpstore_r10+0,refldamp,dmpstore_r10+1
interp dmpstore_r10+2,dmpstore_r10+1,refldamp,dmpstore_r10+2
interp dmpstore_l11+0,readl11,refldamp,dmpstore_l11+0
interp dmpstore_l11+1,dmpstore_l11+0,refldamp,dmpstore_l11+1
interp dmpstore_r12+0,readr12,refldamp,dmpstore_r12+0
interp dmpstore_r12+1,dmpstore_r12+0,refldamp,dmpstore_r12+1
interp dmpstore_l13+0,readl13,refldamp,dmpstore_l13+0
interp dmpstore_r14+0,readr14,refldamp,dmpstore_r14+0
interp dmpstore_l15+0,readl15,refldamp,dmpstore_l15+0
interp dmpstore_l15+1,dmpstore_l15+0,refldamp,dmpstore_l15+1
interp dmpstore_r16+0,readr16,refldamp,dmpstore_r16+0
interp dmpstore_r16+1,dmpstore_r16+0,refldamp,dmpstore_r16+1
interp dmpstore_r17+0,readr17,refldamp,dmpstore_r17+0
interp dmpstore_r17+1,dmpstore_r17+0,refldamp,dmpstore_r17+1
interp dmpstore_r17+2,dmpstore_r17+1,refldamp,dmpstore_r17+2
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_l0+2,fr0
macmv tmp,C_0,dmpstore_r0+2,fl0
macmv tmp,C_0,dmpstore_r1+2,fr1
macmv tmp,C_0,dmpstore_l1+2,fl1
macmv tmp,C_0,dmpstore_l2+1,fr2
macmv tmp,C_0,dmpstore_r2+1,fl2
macmv tmp,C_0,dmpstore_r3+1,fr3
macmv tmp,C_0,dmpstore_l3+1,fl3
macmv tmp,C_0,dmpstore_l4+0,fr4
macmv tmp,C_0,dmpstore_r4+0,fl4
macmv tmp,C_0,dmpstore_r5+0,fr5
macmv tmp,C_0,dmpstore_l5+0,fl5
macmv tmp,C_0,dmpstore_l6+0,fr6
macmv tmp,C_0,dmpstore_r6+0,fl6
macmv tmp,C_0,dmpstore_r7+0,fr7
macmv tmp,C_0,dmpstore_l7+0,fl7
macmv tmp,C_0,dmpstore_l8+1,fr8
macmv tmp,C_0,dmpstore_r8+1,fl8
macmv tmp,C_0,dmpstore_r9+1,fr9
macmv tmp,C_0,dmpstore_l9+1,fl9
macmv tmp,C_0,dmpstore_r10+2,fr10
macmv tmp,C_0,dmpstore_l11+1,fr11
macmv tmp,C_0,dmpstore_r12+1,fr12
macmv tmp,C_0,dmpstore_l13+0,fr13
macmv tmp,C_0,dmpstore_r14+0,fr14
macmv tmp,C_0,dmpstore_l15+1,fr15
macmv tmp,C_0,dmpstore_r16+1,fr16
macs fvrefl_fr,ACCUM,dmpstore_r17+2,fr17
;;; Accumulate reflections for RL
interp dmpstore_l10+0,readl10,refldamp,dmpstore_l10+0
interp dmpstore_l10+1,dmpstore_l10+0,refldamp,dmpstore_l10+1
interp dmpstore_l10+2,dmpstore_l10+1,refldamp,dmpstore_l10+2
interp dmpstore_r11+0,readr11,refldamp,dmpstore_r11+0
interp dmpstore_r11+1,dmpstore_r11+0,refldamp,dmpstore_r11+1
interp dmpstore_l12+0,readl12,refldamp,dmpstore_l12+0
interp dmpstore_l12+1,dmpstore_l12+0,refldamp,dmpstore_l12+1
interp dmpstore_r13+0,readr13,refldamp,dmpstore_r13+0
interp dmpstore_l14+0,readl14,refldamp,dmpstore_l14+0
interp dmpstore_r15+0,readr15,refldamp,dmpstore_r15+0
interp dmpstore_r15+1,dmpstore_r15+0,refldamp,dmpstore_r15+1
interp dmpstore_l16+0,readl16,refldamp,dmpstore_l16+0
interp dmpstore_l16+1,dmpstore_l16+0,refldamp,dmpstore_l16+1
interp dmpstore_l17+0,readl17,refldamp,dmpstore_l17+0
interp dmpstore_l17+1,dmpstore_l17+0,refldamp,dmpstore_l17+1
interp dmpstore_l17+2,dmpstore_l17+1,refldamp,dmpstore_l17+2
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_l10+2,rr10
macmv tmp,C_0,dmpstore_r11+1,rr11
macmv tmp,C_0,dmpstore_l12+1,rr12
macmv tmp,C_0,dmpstore_r13+0,rr13
macmv tmp,C_0,dmpstore_l14+0,rr14
macmv tmp,C_0,dmpstore_r15+1,rr15
macmv tmp,C_0,dmpstore_l16+1,rr16
macs fvrefl_rl,ACCUM,dmpstore_l17+2,rr17
;;; Accumulate reflections for RR
interp dmpstore_r10+0,readr10,refldamp,dmpstore_r10+0
interp dmpstore_r10+1,dmpstore_r10+0,refldamp,dmpstore_r10+1
interp dmpstore_r10+2,dmpstore_r10+1,refldamp,dmpstore_r10+2
interp dmpstore_l11+0,readl11,refldamp,dmpstore_l11+0
interp dmpstore_l11+1,dmpstore_l11+0,refldamp,dmpstore_l11+1
interp dmpstore_r12+0,readr12,refldamp,dmpstore_r12+0
interp dmpstore_r12+1,dmpstore_r12+0,refldamp,dmpstore_r12+1
interp dmpstore_l13+0,readl13,refldamp,dmpstore_l13+0
interp dmpstore_r14+0,readr14,refldamp,dmpstore_r14+0
interp dmpstore_l15+0,readl15,refldamp,dmpstore_l15+0
interp dmpstore_l15+1,dmpstore_l15+0,refldamp,dmpstore_l15+1
interp dmpstore_r16+0,readr16,refldamp,dmpstore_r16+0
interp dmpstore_r16+1,dmpstore_r16+0,refldamp,dmpstore_r16+1
interp dmpstore_r17+0,readr17,refldamp,dmpstore_r17+0
interp dmpstore_r17+1,dmpstore_r17+0,refldamp,dmpstore_r17+1
interp dmpstore_r17+2,dmpstore_r17+1,refldamp,dmpstore_r17+2
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_r10+2,rr10
macmv tmp,C_0,dmpstore_l11+1,rr11
macmv tmp,C_0,dmpstore_r12+1,rr12
macmv tmp,C_0,dmpstore_l13+0,rr13
macmv tmp,C_0,dmpstore_r14+0,rr14
macmv tmp,C_0,dmpstore_l15+1,rr15
macmv tmp,C_0,dmpstore_r16+1,rr16
macs fvrefl_rr,ACCUM,dmpstore_r17+2,rr17
END

View file

@ -0,0 +1,320 @@
;;; FV10K1 room relections code
;;; Generates room reflections according to file default.room.rp, and stores
;;; them in GPRs fvrefl_[fl|fr|rl|rr].
;;; Built on Sat Jan 24 13:18:00 2004 from room definition file default.room.rp.
; define delays and dampening constants
readr0 tread dlyr,&0.003511
readl0 tread dlyl,&0.003511
fl0 constant #-0.371429
fr0 constant #-0.092857
dmpstore_r0 sta 0
dmpstore_l0 sta 0
readr1 tread dlyr,&0.003511
readl1 tread dlyl,&0.003511
fl1 constant #-0.092857
fr1 constant #-0.371429
dmpstore_r1 sta 0
dmpstore_l1 sta 0
readr2 tread dlyr,&0.006548
readl2 tread dlyl,&0.006548
fr2 constant #-0.508333
dmpstore_r2 sta 0
dmpstore_l2 sta 0
readr3 tread dlyr,&0.007252
readl3 tread dlyl,&0.007252
fl3 constant #-0.298947
fr3 constant #-0.074737
dmpstore_r3 sta 0
dmpstore_l3 sta 0
readr4 tread dlyr,&0.007252
readl4 tread dlyl,&0.007252
fl4 constant #-0.074737
fr4 constant #-0.298947
dmpstore_r4 sta 0
dmpstore_l4 sta 0
readr5 tread dlyr,&0.009261
readl5 tread dlyl,&0.009261
fr5 constant #0.270341
dmpstore_r5 sta 0,0
dmpstore_l5 sta 0,0
readr6 tread dlyr,&0.012327
readl6 tread dlyl,&0.012327
fr6 constant #0.240611
dmpstore_r6 sta 0,0
dmpstore_l6 sta 0,0
readr7 tread dlyr,&0.016174
readl7 tread dlyl,&0.016174
fr7 constant #-0.253287
rr7 constant #-0.015830
dmpstore_r7 sta 0
dmpstore_l7 sta 0
readr8 tread dlyr,&0.016690
readl8 tread dlyl,&0.016690
fl8 constant #0.105486
fr8 constant #0.026371
dmpstore_r8 sta 0,0
dmpstore_l8 sta 0,0
readr9 tread dlyr,&0.016690
readl9 tread dlyl,&0.016690
fl9 constant #0.026371
fr9 constant #0.105486
dmpstore_r9 sta 0,0
dmpstore_l9 sta 0,0
readr10 tread dlyr,&0.016690
readl10 tread dlyl,&0.016690
fl10 constant #0.105486
fr10 constant #0.026371
dmpstore_r10 sta 0,0
dmpstore_l10 sta 0,0
readr11 tread dlyr,&0.016690
readl11 tread dlyl,&0.016690
fl11 constant #0.026371
fr11 constant #0.105486
dmpstore_r11 sta 0,0
dmpstore_l11 sta 0,0
readr12 tread dlyr,&0.018195
readl12 tread dlyl,&0.018195
fr12 constant #0.147307
rr12 constant #0.009207
dmpstore_r12 sta 0,0
dmpstore_l12 sta 0,0
readr13 tread dlyr,&0.020577
readl13 tread dlyl,&0.020577
fr13 constant #-0.098203
dmpstore_r13 sta 0,0,0
dmpstore_l13 sta 0,0,0
readr14 tread dlyr,&0.020577
readl14 tread dlyl,&0.020577
fr14 constant #0.142194
rr14 constant #0.008887
dmpstore_r14 sta 0,0
dmpstore_l14 sta 0,0
readr15 tread dlyr,&0.020577
readl15 tread dlyl,&0.020577
fr15 constant #-0.098203
dmpstore_r15 sta 0,0,0
dmpstore_l15 sta 0,0,0
readr16 tread dlyr,&0.021591
readl16 tread dlyl,&0.021591
rl16 constant #-0.130920
rr16 constant #-0.071413
dmpstore_r16 sta 0
dmpstore_l16 sta 0
readr17 tread dlyr,&0.021591
readl17 tread dlyl,&0.021591
rl17 constant #-0.071413
rr17 constant #-0.130920
dmpstore_r17 sta 0
dmpstore_l17 sta 0
readr18 tread dlyr,&0.023355
readl18 tread dlyl,&0.023355
rl18 constant #0.078182
rr18 constant #0.042646
dmpstore_r18 sta 0,0
dmpstore_l18 sta 0,0
readr19 tread dlyr,&0.023355
readl19 tread dlyl,&0.023355
rl19 constant #0.042646
rr19 constant #0.078182
dmpstore_r19 sta 0,0
dmpstore_l19 sta 0,0
;;; Accumulate reflections for FL
interp dmpstore_l0+0,readl0,refldamp,dmpstore_l0+0
interp dmpstore_r0+0,readr0,refldamp,dmpstore_r0+0
interp dmpstore_r1+0,readr1,refldamp,dmpstore_r1+0
interp dmpstore_l1+0,readl1,refldamp,dmpstore_l1+0
interp dmpstore_l2+0,readl2,refldamp,dmpstore_l2+0
interp dmpstore_l3+0,readl3,refldamp,dmpstore_l3+0
interp dmpstore_r3+0,readr3,refldamp,dmpstore_r3+0
interp dmpstore_r4+0,readr4,refldamp,dmpstore_r4+0
interp dmpstore_l4+0,readl4,refldamp,dmpstore_l4+0
interp dmpstore_l5+0,readl5,refldamp,dmpstore_l5+0
interp dmpstore_l5+1,dmpstore_l5+0,refldamp,dmpstore_l5+1
interp dmpstore_l6+0,readl6,refldamp,dmpstore_l6+0
interp dmpstore_l6+1,dmpstore_l6+0,refldamp,dmpstore_l6+1
interp dmpstore_r7+0,readr7,refldamp,dmpstore_r7+0
interp dmpstore_l8+0,readl8,refldamp,dmpstore_l8+0
interp dmpstore_l8+1,dmpstore_l8+0,refldamp,dmpstore_l8+1
interp dmpstore_r8+0,readr8,refldamp,dmpstore_r8+0
interp dmpstore_r8+1,dmpstore_r8+0,refldamp,dmpstore_r8+1
interp dmpstore_r9+0,readr9,refldamp,dmpstore_r9+0
interp dmpstore_r9+1,dmpstore_r9+0,refldamp,dmpstore_r9+1
interp dmpstore_l9+0,readl9,refldamp,dmpstore_l9+0
interp dmpstore_l9+1,dmpstore_l9+0,refldamp,dmpstore_l9+1
interp dmpstore_l10+0,readl10,refldamp,dmpstore_l10+0
interp dmpstore_l10+1,dmpstore_l10+0,refldamp,dmpstore_l10+1
interp dmpstore_r10+0,readr10,refldamp,dmpstore_r10+0
interp dmpstore_r10+1,dmpstore_r10+0,refldamp,dmpstore_r10+1
interp dmpstore_r11+0,readr11,refldamp,dmpstore_r11+0
interp dmpstore_r11+1,dmpstore_r11+0,refldamp,dmpstore_r11+1
interp dmpstore_l11+0,readl11,refldamp,dmpstore_l11+0
interp dmpstore_l11+1,dmpstore_l11+0,refldamp,dmpstore_l11+1
interp dmpstore_r12+0,readr12,refldamp,dmpstore_r12+0
interp dmpstore_r12+1,dmpstore_r12+0,refldamp,dmpstore_r12+1
interp dmpstore_l13+0,readl13,refldamp,dmpstore_l13+0
interp dmpstore_l13+1,dmpstore_l13+0,refldamp,dmpstore_l13+1
interp dmpstore_l13+2,dmpstore_l13+1,refldamp,dmpstore_l13+2
interp dmpstore_r14+0,readr14,refldamp,dmpstore_r14+0
interp dmpstore_r14+1,dmpstore_r14+0,refldamp,dmpstore_r14+1
interp dmpstore_l15+0,readl15,refldamp,dmpstore_l15+0
interp dmpstore_l15+1,dmpstore_l15+0,refldamp,dmpstore_l15+1
interp dmpstore_l15+2,dmpstore_l15+1,refldamp,dmpstore_l15+2
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_l0+0,fl0
macmv tmp,C_0,dmpstore_r0+0,fr0
macmv tmp,C_0,dmpstore_r1+0,fl1
macmv tmp,C_0,dmpstore_l1+0,fr1
macmv tmp,C_0,dmpstore_l2+0,fr2
macmv tmp,C_0,dmpstore_l3+0,fl3
macmv tmp,C_0,dmpstore_r3+0,fr3
macmv tmp,C_0,dmpstore_r4+0,fl4
macmv tmp,C_0,dmpstore_l4+0,fr4
macmv tmp,C_0,dmpstore_l5+1,fr5
macmv tmp,C_0,dmpstore_l6+1,fr6
macmv tmp,C_0,dmpstore_r7+0,fr7
macmv tmp,C_0,dmpstore_l8+1,fl8
macmv tmp,C_0,dmpstore_r8+1,fr8
macmv tmp,C_0,dmpstore_r9+1,fl9
macmv tmp,C_0,dmpstore_l9+1,fr9
macmv tmp,C_0,dmpstore_l10+1,fl10
macmv tmp,C_0,dmpstore_r10+1,fr10
macmv tmp,C_0,dmpstore_r11+1,fl11
macmv tmp,C_0,dmpstore_l11+1,fr11
macmv tmp,C_0,dmpstore_r12+1,fr12
macmv tmp,C_0,dmpstore_l13+2,fr13
macmv tmp,C_0,dmpstore_r14+1,fr14
macs fvrefl_fl,ACCUM,dmpstore_l15+2,fr15
;;; Accumulate reflections for FR
interp dmpstore_l0+0,readl0,refldamp,dmpstore_l0+0
interp dmpstore_r0+0,readr0,refldamp,dmpstore_r0+0
interp dmpstore_r1+0,readr1,refldamp,dmpstore_r1+0
interp dmpstore_l1+0,readl1,refldamp,dmpstore_l1+0
interp dmpstore_r2+0,readr2,refldamp,dmpstore_r2+0
interp dmpstore_l3+0,readl3,refldamp,dmpstore_l3+0
interp dmpstore_r3+0,readr3,refldamp,dmpstore_r3+0
interp dmpstore_r4+0,readr4,refldamp,dmpstore_r4+0
interp dmpstore_l4+0,readl4,refldamp,dmpstore_l4+0
interp dmpstore_r5+0,readr5,refldamp,dmpstore_r5+0
interp dmpstore_r5+1,dmpstore_r5+0,refldamp,dmpstore_r5+1
interp dmpstore_r6+0,readr6,refldamp,dmpstore_r6+0
interp dmpstore_r6+1,dmpstore_r6+0,refldamp,dmpstore_r6+1
interp dmpstore_l7+0,readl7,refldamp,dmpstore_l7+0
interp dmpstore_l8+0,readl8,refldamp,dmpstore_l8+0
interp dmpstore_l8+1,dmpstore_l8+0,refldamp,dmpstore_l8+1
interp dmpstore_r8+0,readr8,refldamp,dmpstore_r8+0
interp dmpstore_r8+1,dmpstore_r8+0,refldamp,dmpstore_r8+1
interp dmpstore_r9+0,readr9,refldamp,dmpstore_r9+0
interp dmpstore_r9+1,dmpstore_r9+0,refldamp,dmpstore_r9+1
interp dmpstore_l9+0,readl9,refldamp,dmpstore_l9+0
interp dmpstore_l9+1,dmpstore_l9+0,refldamp,dmpstore_l9+1
interp dmpstore_l10+0,readl10,refldamp,dmpstore_l10+0
interp dmpstore_l10+1,dmpstore_l10+0,refldamp,dmpstore_l10+1
interp dmpstore_r10+0,readr10,refldamp,dmpstore_r10+0
interp dmpstore_r10+1,dmpstore_r10+0,refldamp,dmpstore_r10+1
interp dmpstore_r11+0,readr11,refldamp,dmpstore_r11+0
interp dmpstore_r11+1,dmpstore_r11+0,refldamp,dmpstore_r11+1
interp dmpstore_l11+0,readl11,refldamp,dmpstore_l11+0
interp dmpstore_l11+1,dmpstore_l11+0,refldamp,dmpstore_l11+1
interp dmpstore_l12+0,readl12,refldamp,dmpstore_l12+0
interp dmpstore_l12+1,dmpstore_l12+0,refldamp,dmpstore_l12+1
interp dmpstore_r13+0,readr13,refldamp,dmpstore_r13+0
interp dmpstore_r13+1,dmpstore_r13+0,refldamp,dmpstore_r13+1
interp dmpstore_r13+2,dmpstore_r13+1,refldamp,dmpstore_r13+2
interp dmpstore_l14+0,readl14,refldamp,dmpstore_l14+0
interp dmpstore_l14+1,dmpstore_l14+0,refldamp,dmpstore_l14+1
interp dmpstore_r15+0,readr15,refldamp,dmpstore_r15+0
interp dmpstore_r15+1,dmpstore_r15+0,refldamp,dmpstore_r15+1
interp dmpstore_r15+2,dmpstore_r15+1,refldamp,dmpstore_r15+2
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_l0+0,fr0
macmv tmp,C_0,dmpstore_r0+0,fl0
macmv tmp,C_0,dmpstore_r1+0,fr1
macmv tmp,C_0,dmpstore_l1+0,fl1
macmv tmp,C_0,dmpstore_r2+0,fr2
macmv tmp,C_0,dmpstore_l3+0,fr3
macmv tmp,C_0,dmpstore_r3+0,fl3
macmv tmp,C_0,dmpstore_r4+0,fr4
macmv tmp,C_0,dmpstore_l4+0,fl4
macmv tmp,C_0,dmpstore_r5+1,fr5
macmv tmp,C_0,dmpstore_r6+1,fr6
macmv tmp,C_0,dmpstore_l7+0,fr7
macmv tmp,C_0,dmpstore_l8+1,fr8
macmv tmp,C_0,dmpstore_r8+1,fl8
macmv tmp,C_0,dmpstore_r9+1,fr9
macmv tmp,C_0,dmpstore_l9+1,fl9
macmv tmp,C_0,dmpstore_l10+1,fr10
macmv tmp,C_0,dmpstore_r10+1,fl10
macmv tmp,C_0,dmpstore_r11+1,fr11
macmv tmp,C_0,dmpstore_l11+1,fl11
macmv tmp,C_0,dmpstore_l12+1,fr12
macmv tmp,C_0,dmpstore_r13+2,fr13
macmv tmp,C_0,dmpstore_l14+1,fr14
macs fvrefl_fr,ACCUM,dmpstore_r15+2,fr15
;;; Accumulate reflections for RL
interp dmpstore_r7+0,readr7,refldamp,dmpstore_r7+0
interp dmpstore_r12+0,readr12,refldamp,dmpstore_r12+0
interp dmpstore_r12+1,dmpstore_r12+0,refldamp,dmpstore_r12+1
interp dmpstore_r14+0,readr14,refldamp,dmpstore_r14+0
interp dmpstore_r14+1,dmpstore_r14+0,refldamp,dmpstore_r14+1
interp dmpstore_l16+0,readl16,refldamp,dmpstore_l16+0
interp dmpstore_r16+0,readr16,refldamp,dmpstore_r16+0
interp dmpstore_r17+0,readr17,refldamp,dmpstore_r17+0
interp dmpstore_l17+0,readl17,refldamp,dmpstore_l17+0
interp dmpstore_l18+0,readl18,refldamp,dmpstore_l18+0
interp dmpstore_l18+1,dmpstore_l18+0,refldamp,dmpstore_l18+1
interp dmpstore_r18+0,readr18,refldamp,dmpstore_r18+0
interp dmpstore_r18+1,dmpstore_r18+0,refldamp,dmpstore_r18+1
interp dmpstore_r19+0,readr19,refldamp,dmpstore_r19+0
interp dmpstore_r19+1,dmpstore_r19+0,refldamp,dmpstore_r19+1
interp dmpstore_l19+0,readl19,refldamp,dmpstore_l19+0
interp dmpstore_l19+1,dmpstore_l19+0,refldamp,dmpstore_l19+1
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_r7+0,rr7
macmv tmp,C_0,dmpstore_r12+1,rr12
macmv tmp,C_0,dmpstore_r14+1,rr14
macmv tmp,C_0,dmpstore_l16+0,rl16
macmv tmp,C_0,dmpstore_r16+0,rr16
macmv tmp,C_0,dmpstore_r17+0,rl17
macmv tmp,C_0,dmpstore_l17+0,rr17
macmv tmp,C_0,dmpstore_l18+1,rl18
macmv tmp,C_0,dmpstore_r18+1,rr18
macmv tmp,C_0,dmpstore_r19+1,rl19
macs fvrefl_rl,ACCUM,dmpstore_l19+1,rr19
;;; Accumulate reflections for RR
interp dmpstore_l7+0,readl7,refldamp,dmpstore_l7+0
interp dmpstore_l12+0,readl12,refldamp,dmpstore_l12+0
interp dmpstore_l12+1,dmpstore_l12+0,refldamp,dmpstore_l12+1
interp dmpstore_l14+0,readl14,refldamp,dmpstore_l14+0
interp dmpstore_l14+1,dmpstore_l14+0,refldamp,dmpstore_l14+1
interp dmpstore_l16+0,readl16,refldamp,dmpstore_l16+0
interp dmpstore_r16+0,readr16,refldamp,dmpstore_r16+0
interp dmpstore_r17+0,readr17,refldamp,dmpstore_r17+0
interp dmpstore_l17+0,readl17,refldamp,dmpstore_l17+0
interp dmpstore_l18+0,readl18,refldamp,dmpstore_l18+0
interp dmpstore_l18+1,dmpstore_l18+0,refldamp,dmpstore_l18+1
interp dmpstore_r18+0,readr18,refldamp,dmpstore_r18+0
interp dmpstore_r18+1,dmpstore_r18+0,refldamp,dmpstore_r18+1
interp dmpstore_r19+0,readr19,refldamp,dmpstore_r19+0
interp dmpstore_r19+1,dmpstore_r19+0,refldamp,dmpstore_r19+1
interp dmpstore_l19+0,readl19,refldamp,dmpstore_l19+0
interp dmpstore_l19+1,dmpstore_l19+0,refldamp,dmpstore_l19+1
macs C_0,C_0,C_0,C_0 ; reset accumulator
macmv tmp,C_0,dmpstore_l7+0,rr7
macmv tmp,C_0,dmpstore_l12+1,rr12
macmv tmp,C_0,dmpstore_l14+1,rr14
macmv tmp,C_0,dmpstore_l16+0,rr16
macmv tmp,C_0,dmpstore_r16+0,rl16
macmv tmp,C_0,dmpstore_r17+0,rr17
macmv tmp,C_0,dmpstore_l17+0,rl17
macmv tmp,C_0,dmpstore_l18+1,rr18
macmv tmp,C_0,dmpstore_r18+1,rl18
macmv tmp,C_0,dmpstore_r19+1,rr19
macs fvrefl_rr,ACCUM,dmpstore_l19+1,rl19
END

View file

@ -0,0 +1,16 @@
name "volLR"
include "emu_constants.asm"
volLR control #1,0,#1
inl IO
inr IO
outl equ inl
outr equ inr
macs outl,inl.o,inl,volLR
macs outr,inr.o,inr,volLR
end