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326c6802e4
The following patch comes from the realization that at least ARM code
for atomics is quite broken and nobody has cared for a decade.
A quick dive shows that only snd_atomic_{read,write}_{begin,end}
appear to be used widely. These are implemented using wmb/rmb.
Only other use of atomic functions is in pcm_meter.c.
The #SND_PCM_TYPE_METER plugin type appears rarely, if ever, used.
I presume these days anyone who wants a meter/scope will do in pulseaudio
layer instead of alsa.
It would seem better fit to have pcm_meter in alsa-plugins instead
of alsa-lib, but I guess that would be an ABI break...
So instead, I'm proposing here
1. Removal of all hand-crafted atomics from iatomic.h apart from barriers,
which are used in snd_atomic_{read,write}_{begin,end}.
2. Using __sync_synchronize as the default fallback for barriers. This
has been available since gcc 4.1, so it shouldn't be a problem.
3. Defining the few atomics used by pcm_meter.c withing pcm_meter.c
itself, using gcc atomic builtins[1].
4. Since gcc atomic builtins are available only since gcc 4.7, add a check for
that in gcc configure.in, and don't build pcm meter plugin if using
older gcc.
The last point has the impact, that if there actually is someone who 1)
uses the meter plugin 2) wants to upgrade to 2014 alsa-lib 3) but
does not want to use a 2012+ gcc - that someone will be inconvenienced.
Finally remove the unneeded configure check for cpu type. We can
trust the gcc to set right flags for us.
[1] http://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
170 lines
4.5 KiB
C
170 lines
4.5 KiB
C
#ifndef __ALSA_IATOMIC_H
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#define __ALSA_IATOMIC_H
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#ifdef __i386__
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#define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#define IATOMIC_DEFINED 1
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#endif
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#ifdef __x86_64__
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence":::"memory")
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#define IATOMIC_DEFINED 1
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#endif
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#ifdef __ia64__
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/*
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* Macros to force memory ordering. In these descriptions, "previous"
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* and "subsequent" refer to program order; "visible" means that all
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* architecturally visible effects of a memory access have occurred
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* (at a minimum, this means the memory has been read or written).
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*
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* wmb(): Guarantees that all preceding stores to memory-
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* like regions are visible before any subsequent
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* stores and that all following stores will be
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* visible only after all previous stores.
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* rmb(): Like wmb(), but for reads.
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* mb(): wmb()/rmb() combo, i.e., all previous memory
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* accesses are visible before all subsequent
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* accesses and vice versa. This is also known as
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* a "fence."
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*
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* Note: "mb()" and its variants cannot be used as a fence to order
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* accesses to memory mapped I/O registers. For that, mf.a needs to
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* be used. However, we don't want to always use mf.a because (a)
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* it's (presumably) much slower than mf and (b) mf.a is supported for
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* sequential memory pages only.
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*/
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#define mb() __asm__ __volatile__ ("mf" ::: "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define IATOMIC_DEFINED 1
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#endif /* __ia64__ */
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#ifdef __alpha__
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#define mb() \
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__asm__ __volatile__("mb": : :"memory")
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#define rmb() \
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__asm__ __volatile__("mb": : :"memory")
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#define wmb() \
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__asm__ __volatile__("wmb": : :"memory")
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#define IATOMIC_DEFINED 1
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#endif /* __alpha__ */
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#ifdef __powerpc__
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/*
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* Memory barrier.
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* The sync instruction guarantees that all memory accesses initiated
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* by this processor have been performed (with respect to all other
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* mechanisms that access memory). The eieio instruction is a barrier
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* providing an ordering (separately) for (a) cacheable stores and (b)
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* loads and stores to non-cacheable memory (e.g. I/O devices).
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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*
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* We can use the eieio instruction for wmb, but since it doesn't
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* give any ordering guarantees about loads, we have to use the
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* stronger but slower sync instruction for mb and rmb.
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*/
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#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("eieio" : : : "memory")
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#define IATOMIC_DEFINED 1
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#endif /* __powerpc__ */
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#ifndef IATOMIC_DEFINED
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/* Generic __sync_synchronize is available from gcc 4.1 */
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#define mb() __sync_synchronize()
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#define rmb() mb()
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#define wmb() mb()
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#define IATOMIC_DEFINED 1
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#endif /* IATOMIC_DEFINED */
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/*
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* Atomic read/write
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* Copyright (c) 2001 by Abramo Bagnara <abramo@alsa-project.org>
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*/
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/* Max number of times we must spin on a spin-lock calling sched_yield().
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After MAX_SPIN_COUNT iterations, we put the calling thread to sleep. */
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#ifndef MAX_SPIN_COUNT
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#define MAX_SPIN_COUNT 50
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#endif
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/* Duration of sleep (in nanoseconds) when we can't acquire a spin-lock
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after MAX_SPIN_COUNT iterations of sched_yield().
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This MUST BE > 2ms.
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(Otherwise the kernel does busy-waiting for real-time threads,
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giving other threads no chance to run.) */
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#ifndef SPIN_SLEEP_DURATION
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#define SPIN_SLEEP_DURATION 2000001
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#endif
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typedef struct {
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unsigned int begin, end;
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} snd_atomic_write_t;
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typedef struct {
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volatile const snd_atomic_write_t *write;
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unsigned int end;
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} snd_atomic_read_t;
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void snd_atomic_read_wait(snd_atomic_read_t *t);
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static __inline__ void snd_atomic_write_init(snd_atomic_write_t *w)
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{
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w->begin = 0;
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w->end = 0;
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}
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static __inline__ void snd_atomic_write_begin(snd_atomic_write_t *w)
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{
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w->begin++;
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wmb();
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}
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static __inline__ void snd_atomic_write_end(snd_atomic_write_t *w)
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{
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wmb();
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w->end++;
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}
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static __inline__ void snd_atomic_read_init(snd_atomic_read_t *r, snd_atomic_write_t *w)
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{
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r->write = w;
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}
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static __inline__ void snd_atomic_read_begin(snd_atomic_read_t *r)
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{
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r->end = r->write->end;
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rmb();
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}
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static __inline__ int snd_atomic_read_ok(snd_atomic_read_t *r)
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{
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rmb();
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return r->end == r->write->begin;
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}
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#endif /* __ALSA_IATOMIC_H */
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