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ASoC: topology: Add definitions for mclk_direction values

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Current comment makes not clear the direction of mclk. Previously, similar
description caused a misunderstanding for bclk_master and fsync_master.

This commit solves the potential confusion the same way it is solved for
bclk_master and fsync_master.

Signed-off-by: Kirill Marinushkin <k.marinushkin@gmail.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Mark Brown <broonie@kernel.org>
Cc: Pan Xiuli <xiuli.pan@linux.intel.com>
Cc: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Cc: alsa-devel@alsa-project.org
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Kirill Marinushkin 2018-04-16 20:26:40 +02:00 • committed by Takashi Iwai
parent bdb709ab2a
commit 7cf73b56e4
3 changed files with 19 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

6
include/sound/asoc.h
View file

@ -140,6 +140,10 @@
#define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1
#define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2
/* DAI mclk_direction */
#define SND_SOC_TPLG_MCLK_CO 0 /* for codec, mclk is output */
#define SND_SOC_TPLG_MCLK_CI 1 /* for codec, mclk is input */
/* DAI physical PCM data formats.
* Add new formats to the end of the list.
*/
@ -330,7 +334,7 @@ struct snd_soc_tplg_hw_config {
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
__u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
__u8 mclk_direction; /* 0 for input, 1 for output */
__u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
__le16 reserved; /* for 32bit alignment */
__le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */
__le32 bclk_rate; /* BCLK freqency in Hz */

2
include/topology.h
View file

@ -1002,7 +1002,7 @@ struct snd_tplg_hw_config_template {
unsigned char invert_fsync; /* 1 for inverted frame clock, 0 for normal */
unsigned char bclk_master; /* SND_SOC_TPLG_BCLK_ value */
unsigned char fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
unsigned char mclk_direction; /* 0 for input, 1 for output */
unsigned char mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
unsigned short reserved; /* for 32bit alignment */
unsigned int mclk_rate; /* MCLK or SYSCLK freqency in Hz */
unsigned int bclk_rate; /* BCLK freqency in Hz */

15
src/topology/pcm.c
View file

@ -1223,8 +1223,19 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
if (snd_config_get_string(n, &val) < 0)
return -EINVAL;
if (!strcmp(val, "master"))
hw_cfg->mclk_direction = true;
if (!strcmp(val, "master")) {
/* For backwards capability,
* "master" == "for codec, mclk is input"
*/
SNDERR("warning: deprecated mclk value '%s'\n",
val);
hw_cfg->mclk_direction = SND_SOC_TPLG_MCLK_CI;
} else if (!strcmp(val, "codec_mclk_in")) {
hw_cfg->mclk_direction = SND_SOC_TPLG_MCLK_CI;
} else if (!strcmp(val, "codec_mclk_out")) {
hw_cfg->mclk_direction = SND_SOC_TPLG_MCLK_CO;
}
continue;
}