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topology: use inclusive language for bclk

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use bclk_provider for structure fields, 'codec_provider' and
'codec_consumer' for options and modify #defines to use CP and CC
suffixes.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Pierre-Louis Bossart 2020-11-12 10:29:38 -06:00 • committed by Takashi Iwai
parent 2757191e3b
commit 39bd0e1a5b
3 changed files with 34 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

11
include/sound/uapi/asoc.h
View file

@ -169,10 +169,13 @@
#define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3) #define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3)
/* DAI topology BCLK parameter /* DAI topology BCLK parameter
* For the backwards capability, by default codec is bclk master * For the backwards capability, by default codec is bclk provider
*/ */
#define SND_SOC_TPLG_BCLK_CM 0 /* codec is bclk master */ #define SND_SOC_TPLG_BCLK_CP 0 /* codec is bclk provider */
#define SND_SOC_TPLG_BCLK_CS 1 /* codec is bclk slave */ #define SND_SOC_TPLG_BCLK_CC 1 /* codec is bclk consumer */
/* keep previous definitions for compatibility */
#define SND_SOC_TPLG_BCLK_CM SND_SOC_TPLG_BCLK_CP
#define SND_SOC_TPLG_BCLK_CS SND_SOC_TPLG_BCLK_CC
/* DAI topology FSYNC parameter /* DAI topology FSYNC parameter
* For the backwards capability, by default codec is fsync master * For the backwards capability, by default codec is fsync master
@ -335,7 +338,7 @@ struct snd_soc_tplg_hw_config {
__u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */ __u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */ __u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */ __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */ __u8 bclk_provider; /* SND_SOC_TPLG_BCLK_ value */
__u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */ __u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
__u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */ __u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
__le16 reserved; /* for 32bit alignment */ __le16 reserved; /* for 32bit alignment */

2
include/topology.h
View file

@ -1028,7 +1028,7 @@ struct snd_tplg_hw_config_template {
unsigned char clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */ unsigned char clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
unsigned char invert_bclk; /* 1 for inverted BCLK, 0 for normal */ unsigned char invert_bclk; /* 1 for inverted BCLK, 0 for normal */
unsigned char invert_fsync; /* 1 for inverted frame clock, 0 for normal */ unsigned char invert_fsync; /* 1 for inverted frame clock, 0 for normal */
unsigned char bclk_master; /* SND_SOC_TPLG_BCLK_ value */ unsigned char bclk_provider; /* SND_SOC_TPLG_BCLK_ value */
unsigned char fsync_master; /* SND_SOC_TPLG_FSYNC_ value */ unsigned char fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
unsigned char mclk_direction; /* SND_SOC_TPLG_MCLK_ value */ unsigned char mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
unsigned short reserved; /* for 32bit alignment */ unsigned short reserved; /* for 32bit alignment */

36
src/topology/pcm.c
View file

@ -1411,6 +1411,7 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
snd_config_t *n; snd_config_t *n;
const char *id, *val = NULL; const char *id, *val = NULL;
int ret, ival; int ret, ival;
bool provider_legacy;
elem = tplg_elem_new_common(tplg, cfg, NULL, SND_TPLG_TYPE_HW_CONFIG); elem = tplg_elem_new_common(tplg, cfg, NULL, SND_TPLG_TYPE_HW_CONFIG);
if (!elem) if (!elem)
@ -1451,8 +1452,15 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
continue; continue;
} }
if (strcmp(id, "bclk") == 0 || provider_legacy = false;
strcmp(id, "bclk_master") == 0) { if (strcmp(id, "bclk_master") == 0) {
SNDERR("deprecated option %s, please use 'bclk'\n", id);
provider_legacy = true;
}
if (provider_legacy ||
strcmp(id, "bclk") == 0) {
if (snd_config_get_string(n, &val) < 0) if (snd_config_get_string(n, &val) < 0)
return -EINVAL; return -EINVAL;
@ -1462,11 +1470,19 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
*/ */
SNDERR("deprecated bclk value '%s'", val); SNDERR("deprecated bclk value '%s'", val);
hw_cfg->bclk_master = SND_SOC_TPLG_BCLK_CS; hw_cfg->bclk_provider = SND_SOC_TPLG_BCLK_CC;
} else if (!strcmp(val, "codec_slave")) { } else if (!strcmp(val, "codec_slave")) {
hw_cfg->bclk_master = SND_SOC_TPLG_BCLK_CS; SNDERR("deprecated bclk value '%s', use 'codec_consumer'", val);
hw_cfg->bclk_provider = SND_SOC_TPLG_BCLK_CC;
} else if (!strcmp(val, "codec_consumer")) {
hw_cfg->bclk_provider = SND_SOC_TPLG_BCLK_CC;
} else if (!strcmp(val, "codec_master")) { } else if (!strcmp(val, "codec_master")) {
hw_cfg->bclk_master = SND_SOC_TPLG_BCLK_CM; SNDERR("deprecated bclk value '%s', use 'codec_provider", val);
hw_cfg->bclk_provider = SND_SOC_TPLG_BCLK_CP;
} else if (!strcmp(val, "codec_provider")) {
hw_cfg->bclk_provider = SND_SOC_TPLG_BCLK_CP;
} }
continue; continue;
} }
@ -1623,10 +1639,10 @@ int tplg_save_hw_config(snd_tplg_t *tplg ATTRIBUTE_UNUSED,
if (err >= 0 && hc->fmt) if (err >= 0 && hc->fmt)
err = tplg_save_printf(dst, pfx, "\tformat '%s'\n", err = tplg_save_printf(dst, pfx, "\tformat '%s'\n",
get_audio_hw_format_name(hc->fmt)); get_audio_hw_format_name(hc->fmt));
if (err >= 0 && hc->bclk_master) if (err >= 0 && hc->bclk_provider)
err = tplg_save_printf(dst, pfx, "\tbclk '%s'\n", err = tplg_save_printf(dst, pfx, "\tbclk '%s'\n",
hc->bclk_master == SND_SOC_TPLG_BCLK_CS ? hc->bclk_provider == SND_SOC_TPLG_BCLK_CC ?
"codec_slave" : "codec_master"); "codec_consumer" : "codec_provider");
if (err >= 0 && hc->bclk_rate) if (err >= 0 && hc->bclk_rate)
err = tplg_save_printf(dst, pfx, "\tbclk_freq %u\n", err = tplg_save_printf(dst, pfx, "\tbclk_freq %u\n",
hc->bclk_rate); hc->bclk_rate);
@ -1791,7 +1807,7 @@ static int set_link_hw_config(struct snd_soc_tplg_hw_config *cfg,
cfg->clock_gated = tpl->clock_gated; cfg->clock_gated = tpl->clock_gated;
cfg->invert_bclk = tpl->invert_bclk; cfg->invert_bclk = tpl->invert_bclk;
cfg->invert_fsync = tpl->invert_fsync; cfg->invert_fsync = tpl->invert_fsync;
cfg->bclk_master = tpl->bclk_master; cfg->bclk_provider = tpl->bclk_provider;
cfg->fsync_master = tpl->fsync_master; cfg->fsync_master = tpl->fsync_master;
cfg->mclk_direction = tpl->mclk_direction; cfg->mclk_direction = tpl->mclk_direction;
cfg->reserved = tpl->reserved; cfg->reserved = tpl->reserved;
@ -2174,7 +2190,7 @@ next:
hw->clock_gated = link->hw_config[i].clock_gated; hw->clock_gated = link->hw_config[i].clock_gated;
hw->invert_bclk = link->hw_config[i].invert_bclk; hw->invert_bclk = link->hw_config[i].invert_bclk;
hw->invert_fsync = link->hw_config[i].invert_fsync; hw->invert_fsync = link->hw_config[i].invert_fsync;
hw->bclk_master = link->hw_config[i].bclk_master; hw->bclk_provider = link->hw_config[i].bclk_provider;
hw->fsync_master = link->hw_config[i].fsync_master; hw->fsync_master = link->hw_config[i].fsync_master;
hw->mclk_direction = link->hw_config[i].mclk_direction; hw->mclk_direction = link->hw_config[i].mclk_direction;
hw->mclk_rate = link->hw_config[i].mclk_rate; hw->mclk_rate = link->hw_config[i].mclk_rate;