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topology: use inclusive language for bclk

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use bclk_provider for structure fields, 'codec_provider' and
'codec_consumer' for options and modify #defines to use CP and CC
suffixes.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Pierre-Louis Bossart 2020-11-12 10:29:38 -06:00 • committed by Takashi Iwai
parent 2757191e3b
commit 39bd0e1a5b
3 changed files with 34 additions and 15 deletions
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11
include/sound/uapi/asoc.h
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@ -169,10 +169,13 @@
#define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3)
/* DAI topology BCLK parameter
* For the backwards capability, by default codec is bclk master
* For the backwards capability, by default codec is bclk provider
*/
#define SND_SOC_TPLG_BCLK_CM 0 /* codec is bclk master */
#define SND_SOC_TPLG_BCLK_CS 1 /* codec is bclk slave */
#define SND_SOC_TPLG_BCLK_CP 0 /* codec is bclk provider */
#define SND_SOC_TPLG_BCLK_CC 1 /* codec is bclk consumer */
/* keep previous definitions for compatibility */
#define SND_SOC_TPLG_BCLK_CM SND_SOC_TPLG_BCLK_CP
#define SND_SOC_TPLG_BCLK_CS SND_SOC_TPLG_BCLK_CC
/* DAI topology FSYNC parameter
* For the backwards capability, by default codec is fsync master
@ -335,7 +338,7 @@ struct snd_soc_tplg_hw_config {
__u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
__u8 bclk_provider; /* SND_SOC_TPLG_BCLK_ value */
__u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
__u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
__le16 reserved; /* for 32bit alignment */