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ASoC: topology: Fix bclk and fsync inversion in set_link_hw_format()

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The values of bclk and fsync are inverted WRT the codec. But the existing
solution already works for Broadwell, see the alsa-lib config:

`alsa-lib/src/conf/topology/broadwell/broadwell.conf`

This commit provides the backwards-compatible solution to fix this misuse.
This commit goes in pair with the corresponding patch for linux.

Signed-off-by: Kirill Marinushkin <k.marinushkin@gmail.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Tested-by: Pan Xiuli <xiuli.pan@linux.intel.com>
Tested-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Mark Brown <broonie@kernel.org>
Cc: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Cc: linux-kernel@vger.kernel.org
Cc: alsa-devel@alsa-project.org
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Kirill Marinushkin 2018-04-16 20:26:38 +02:00 • committed by Takashi Iwai
parent 17bc74d3a2
commit 3778a30bb0
4 changed files with 44 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

16
include/sound/asoc.h
View file

@ -156,6 +156,18 @@
#define SND_SOC_TPLG_LNK_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2) #define SND_SOC_TPLG_LNK_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2)
#define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3) #define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3)
/* DAI topology BCLK parameter
* For the backwards capability, by default codec is bclk master
*/
#define SND_SOC_TPLG_BCLK_CM 0 /* codec is bclk master */
#define SND_SOC_TPLG_BCLK_CS 1 /* codec is bclk slave */
/* DAI topology FSYNC parameter
* For the backwards capability, by default codec is fsync master
*/
#define SND_SOC_TPLG_FSYNC_CM 0 /* codec is fsync master */
#define SND_SOC_TPLG_FSYNC_CS 1 /* codec is fsync slave */
/* /*
* Block Header. * Block Header.
* This header precedes all object and object arrays below. * This header precedes all object and object arrays below.
@ -311,8 +323,8 @@ struct snd_soc_tplg_hw_config {
__u8 clock_gated; /* 1 if clock can be gated to save power */ __u8 clock_gated; /* 1 if clock can be gated to save power */
__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */ __u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */ __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* 1 for master of BCLK, 0 for slave */ __u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
__u8 fsync_master; /* 1 for master of FSYNC, 0 for slave */ __u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
__u8 mclk_direction; /* 0 for input, 1 for output */ __u8 mclk_direction; /* 0 for input, 1 for output */
__le16 reserved; /* for 32bit alignment */ __le16 reserved; /* for 32bit alignment */
__le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */ __le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */

4
include/topology.h
View file

@ -1000,8 +1000,8 @@ struct snd_tplg_hw_config_template {
unsigned char clock_gated; /* 1 if clock can be gated to save power */ unsigned char clock_gated; /* 1 if clock can be gated to save power */
unsigned char invert_bclk; /* 1 for inverted BCLK, 0 for normal */ unsigned char invert_bclk; /* 1 for inverted BCLK, 0 for normal */
unsigned char invert_fsync; /* 1 for inverted frame clock, 0 for normal */ unsigned char invert_fsync; /* 1 for inverted frame clock, 0 for normal */
unsigned char bclk_master; /* 1 for master of BCLK, 0 for slave */ unsigned char bclk_master; /* SND_SOC_TPLG_BCLK_ value */
unsigned char fsync_master; /* 1 for master of FSYNC, 0 for slave */ unsigned char fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
unsigned char mclk_direction; /* 0 for input, 1 for output */ unsigned char mclk_direction; /* 0 for input, 1 for output */
unsigned short reserved; /* for 32bit alignment */ unsigned short reserved; /* for 32bit alignment */
unsigned int mclk_rate; /* MCLK or SYSCLK freqency in Hz */ unsigned int mclk_rate; /* MCLK or SYSCLK freqency in Hz */

4
src/conf/topology/broadwell/broadwell.conf
View file

@ -393,8 +393,8 @@ SectionGraph."dsp" {
SectionHWConfig."CodecHWConfig" { SectionHWConfig."CodecHWConfig" {
id "1" id "1"
format "I2S" # physical audio format. format "I2S" # physical audio format.
bclk "master" # Platform is master of bit clock bclk "codec_slave" # platform is master of bit clock (codec is slave)
fsync "master" # platform is master of fsync fsync "codec_slave" # platform is master of fsync (codec is slave)
} }
SectionLink."Codec" { SectionLink."Codec" {

30
src/topology/pcm.c
View file

@ -1141,8 +1141,19 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
if (snd_config_get_string(n, &val) < 0) if (snd_config_get_string(n, &val) < 0)
return -EINVAL; return -EINVAL;
if (!strcmp(val, "master")) if (!strcmp(val, "master")) {
hw_cfg->bclk_master = true; /* For backwards capability,
* "master" == "codec is slave"
*/
SNDERR("warning: deprecated bclk value '%s'\n",
val);
hw_cfg->bclk_master = SND_SOC_TPLG_BCLK_CS;
} else if (!strcmp(val, "codec_slave")) {
hw_cfg->bclk_master = SND_SOC_TPLG_BCLK_CS;
} else if (!strcmp(val, "codec_master")) {
hw_cfg->bclk_master = SND_SOC_TPLG_BCLK_CM;
}
continue; continue;
} }
@ -1167,8 +1178,19 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
if (snd_config_get_string(n, &val) < 0) if (snd_config_get_string(n, &val) < 0)
return -EINVAL; return -EINVAL;
if (!strcmp(val, "master")) if (!strcmp(val, "master")) {
hw_cfg->fsync_master = true; /* For backwards capability,
* "master" == "codec is slave"
*/
SNDERR("warning: deprecated fsync value '%s'\n",
val);
hw_cfg->fsync_master = SND_SOC_TPLG_FSYNC_CS;
} else if (!strcmp(val, "codec_slave")) {
hw_cfg->fsync_master = SND_SOC_TPLG_FSYNC_CS;
} else if (!strcmp(val, "codec_master")) {
hw_cfg->fsync_master = SND_SOC_TPLG_FSYNC_CM;
}
continue; continue;
} }